Motorola MCPN750A 用户手册
Block Diagram
http://www.motorola.com/computer/literature
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CompactPCI Bus Interface
The CompactPCI bus interface is provided using the Intel 21554 non-
transparent PCI-to-PCI bridge chip. This device implements a 64-bit
primary data bus and 64-bit secondary data bus interface and is PCI 2.1
compliant. The 21554 provides read/write data buffering in both
directions.
transparent PCI-to-PCI bridge chip. This device implements a 64-bit
primary data bus and 64-bit secondary data bus interface and is PCI 2.1
compliant. The 21554 provides read/write data buffering in both
directions.
Unlike a transparent PCI-to-PCI bridge, such as the 21154, the 21554 is
designed to bridge two processor domains. The system CompactPCI bus is
connected to the primary bus side of the bridge, which is also referred to
as the host domain or the host processor side. The secondary bus interfaces
to the MCPN750A board local PCI bus, referred to as the local domain or
local processor side. The 21554 supports independent primary and
secondary address spaces and address translation between the two
processor domains. The 21554 accepts a Type 0 configuration header and
the configuration space is accessible from both primary and secondary
buses. Refer to the MCPN750A CompactPCI Single Board Computer
Programmers Reference Guide (MCPN750A/PG) for additional
information and programming details.
designed to bridge two processor domains. The system CompactPCI bus is
connected to the primary bus side of the bridge, which is also referred to
as the host domain or the host processor side. The secondary bus interfaces
to the MCPN750A board local PCI bus, referred to as the local domain or
local processor side. The 21554 supports independent primary and
secondary address spaces and address translation between the two
processor domains. The 21554 accepts a Type 0 configuration header and
the configuration space is accessible from both primary and secondary
buses. Refer to the MCPN750A CompactPCI Single Board Computer
Programmers Reference Guide (MCPN750A/PG) for additional
information and programming details.
The 21554 also provides for independent primary and secondary PCI
clocks which means that the MCPN750A SBC has it’s own local
processor/PCI bus clock source independent of the system backplane
clocks.
clocks which means that the MCPN750A SBC has it’s own local
processor/PCI bus clock source independent of the system backplane
clocks.
The 21554 has an I
2
O message unit which enables the local processor to
function as an intelligent I/O processor in an I
2
O capable system. The
device also has an interrupt output for each of the primary and secondary
PCI buses. These interrupts may be asserted by the I
PCI buses. These interrupts may be asserted by the I
2
O messaging unit or
by software writes to an interrupt request register.
The 21554 supports +3.3V or +5V signalling at the PCI buses with a
separate VIO pin for the primary and secondary bus I/O’s. The secondary
bus signalling voltage is tied to +5V for compatibility with +5V PMCs.
The primary bus signalling voltage is tied to the CPCI bus VIO, so the
MCPN750A is a universal board that may operate in a +3.3V or +5V
chassis.
separate VIO pin for the primary and secondary bus I/O’s. The secondary
bus signalling voltage is tied to +5V for compatibility with +5V PMCs.
The primary bus signalling voltage is tied to the CPCI bus VIO, so the
MCPN750A is a universal board that may operate in a +3.3V or +5V
chassis.