Motorola CPCI-6020 用户手册
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
Functional Description
PCI Bus A Resources
84
The 82551IT interfaces to an AT93C46 serial EEPROM device which provides power up
configuration information for the 82551IT. This is a 1 KB device organized as 64 16-bit words.
Refer to the corresponding VPD information in
configuration information for the 82551IT. This is a 1 KB device organized as 64 16-bit words.
Refer to the corresponding VPD information in
for the
contents of this device.
4.3.1.4
ISA Bridge, Including EIDE Function
The CPCI-6020 uses the Winbond W83C554F Peripheral Bus Controller (PBC) device to
interface to ISA and EIDE devices, and for additional system resources. The PBC provides the
following additional features:
interface to ISA and EIDE devices, and for additional system resources. The PBC provides the
following additional features:
z
ISA Bus arbitration for DMA devices
z
Functionality of two 82C59 Interrupt Controllers to support 14 ISA interrupts
z
Edge/Level control for ISA interrupts
z
Steerable PCI interrupts (Note: Feature not used. Interrupt steering is via the Harrier ASIC)
z
Seven independently programmable DMA channels (functionality of two 82C37SA devices)
z
Three interval Counter/Timer (82C54 functionality)
4.3.1.5
EIDE Interface
The PBC EIDE interface is capable of accelerated PIO transfers, as well as acting as a PCI Bus
master on behalf of an IDE DMA slave device. This resource provides a primary and secondary
EIDE interface for up to four EIDE devices, and also supports ATAPI-compliant devices.
master on behalf of an IDE DMA slave device. This resource provides a primary and secondary
EIDE interface for up to four EIDE devices, and also supports ATAPI-compliant devices.
The primary EIDE interface is routed to the CompactFLASH memory card. The secondary
EIDE interface is routed to the J5 User I/O connector for interfacing to external EIDE devices.
EIDE interface is routed to the J5 User I/O connector for interfacing to external EIDE devices.
Some Motorola HA chassis route the EIDE Bus across the backplane to the peripheral bay. The
secondary EIDE interface is implemented in such a way to support these chassis. This includes
short traces matched in length, targeted impedance of 80 ohms and onboard termination.
secondary EIDE interface is implemented in such a way to support these chassis. This includes
short traces matched in length, targeted impedance of 80 ohms and onboard termination.
4.3.1.6
ISA Bus Resources
The PBC provides an ISA Bus compatible master and slave interface. The ISA interface
supports the following types of cycles:
supports the following types of cycles:
z
PCI master initiated I/O and memory cycles to the ISA Bus
z
DMA compatible cycles between main memory and ISA I/O
z
ISA master initiated memory cycles to PCI and ISA master initiated I/O cycles to internal
PBC registers
PBC registers
4.3.1.7
Synchronous Serial Ports
The two sync/async ports are implemented with the Z85230 ESCC. Since the Z85230 does not
have all modem control lines, a Z8536 CIO is used to provide the missing modem lines.
have all modem control lines, a Z8536 CIO is used to provide the missing modem lines.
A PLD device is used to perform decode for the Z85230 and the Z8536 for register accesses
and pseudo interrupt acknowledge cycles in ISA I/O space. DMA support for the Z85230 is
provided by the PBC.
and pseudo interrupt acknowledge cycles in ISA I/O space. DMA support for the Z85230 is
provided by the PBC.