Motorola CPCI-6020 用户手册
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
Functional Description
Other Board Resources
94
asserted. The output of Harrier A Watchdog Timer 1 is routed to a Harrier A MPIC interrupt. The
output of Harrier A Watchdog Timer 2 may be optionally routed by means of a build option to a
Harrier A MPIC interrupt or to provide a board hard reset. The standard CPCI-6020 product will
be built to provide hard reset.
output of Harrier A Watchdog Timer 2 may be optionally routed by means of a build option to a
Harrier A MPIC interrupt or to provide a board hard reset. The standard CPCI-6020 product will
be built to provide hard reset.
The output of Harrier B Watchdog Timer 1 and 2 are routed to a Harrier B MPIC interrupt.
Following a Harrier device reset, WDT1 is enabled with a default time-out of 8 seconds and
WDT 2 is enabled with a default time-out of 16 seconds. Each timer must be disabled or
reloaded by software to prevent a time-out. Software may reload a new timer value or force the
timer to reload a previously loaded value. To disable or load/reload a timer requires a two step
process. Refer to the Harrier specification for additional timer details
WDT 2 is enabled with a default time-out of 16 seconds. Each timer must be disabled or
reloaded by software to prevent a time-out. Software may reload a new timer value or force the
timer to reload a previously loaded value. To disable or load/reload a timer requires a two step
process. Refer to the Harrier specification for additional timer details
4.10
Other Board Resources
The following subsections describe other resources that are available on the CPCI-6020.
4.10.1
Miscellaneous Control and Status
The Harrier ASIC contains a Miscellaneous Control and Status register that provides the CPCI-
6020 with the board fail LED control, PrPMC EREADY pin status, board reset control, and
processor timebase enable control. Refer to the Harrier Application Specific Integrated Circuit
(ASIC) Programmer’s Reference Guide for additional details.
6020 with the board fail LED control, PrPMC EREADY pin status, board reset control, and
processor timebase enable control. Refer to the Harrier Application Specific Integrated Circuit
(ASIC) Programmer’s Reference Guide for additional details.
4.10.2
Clock Generator
The CPCI-6020 clock generator uses an MPC9772 PLL clock driver in conjunction with an
MPC93R52 zero delay buffer to provide the clocks for the processor, both Harrier ASICs, the
SDRAMs and all PCI devices. The PPC-to-PCI clock ratios which are support by the CPCI-6020
are shown in the table below. The PCI Bus A runs at a fixed speed of 33 MHz. On board logic
uses the state of the PMC M66EN pin to determine if the PCI Bus B clock frequency will be 33
MHz or 66 MHz. The maximum PPC Bus frequency (66 MHz or 100 MHz) is determined at
board assembly time by populating the appropriate select resistors. The 100 MHz bus mode will
be the standard configuration.
MPC93R52 zero delay buffer to provide the clocks for the processor, both Harrier ASICs, the
SDRAMs and all PCI devices. The PPC-to-PCI clock ratios which are support by the CPCI-6020
are shown in the table below. The PCI Bus A runs at a fixed speed of 33 MHz. On board logic
uses the state of the PMC M66EN pin to determine if the PCI Bus B clock frequency will be 33
MHz or 66 MHz. The maximum PPC Bus frequency (66 MHz or 100 MHz) is determined at
board assembly time by populating the appropriate select resistors. The 100 MHz bus mode will
be the standard configuration.
Table 4-5 PPC to PCI Clock Ratios
PPC Clock Frequency
(MHz)
(MHz)
PCI Clock Frequency
(MHz)
(MHz)
Ratio (PPC:PCI)
Harrier PCI Clock
Divisor (N)
Divisor (N)
100
33.33
3:1
12
66.67
3:2
6
66.67
33.33
2:1
8
66.67
1:1
4