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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
Interrupt Request Register (IRR)
There is a Interrupt Request Register (IRR) for each processor. The IRR
always passes the output of the IS except during Interrupt Acknowledge
cycles. This guarantees that the vector which is read from the Interrupt
Acknowledge Register does not change due to the arrival of a higher
priority interrupt. The IRR also serves as a pipeline register for the two tick
propagation time through the IS.
always passes the output of the IS except during Interrupt Acknowledge
cycles. This guarantees that the vector which is read from the Interrupt
Acknowledge Register does not change due to the arrival of a higher
priority interrupt. The IRR also serves as a pipeline register for the two tick
propagation time through the IS.
In-Service Register (ISR)
There is a In-Service Register (ISR) for each processor. The contents of the
ISR are the priority and source of all interrupts, which are in-service. The
ISR receives a bit-set command during Interrupt Acknowledge cycles and
a bit-clear command during End Of Interrupt cycles.
ISR are the priority and source of all interrupts, which are in-service. The
ISR receives a bit-set command during Interrupt Acknowledge cycles and
a bit-clear command during End Of Interrupt cycles.
The ISR is implemented as a 40 bit register with individual bit set and clear
functions. Fifteen bits are used to store the priority level of each interrupt
which is in-service. Twenty-five bits are used to store the source
identification of each interrupt which is in service. Therefore, there is one
bit for each possible interrupt priority and one bit for each possible
interrupt source.
functions. Fifteen bits are used to store the priority level of each interrupt
which is in-service. Twenty-five bits are used to store the source
identification of each interrupt which is in service. Therefore, there is one
bit for each possible interrupt priority and one bit for each possible
interrupt source.
Interrupt Router
The Interrupt Router monitors the outputs from the ISR’s, Current Task
Priority Registers, Destination Registers, and the IRR’s to determine when
to assert a processor’s INT pin.
Priority Registers, Destination Registers, and the IRR’s to determine when
to assert a processor’s INT pin.
When considering the following rule sets, it is important to remember that
there are two types of inputs to the Interrupt Selectors. If the interrupt is a
distributed class interrupt, there is a single bit in the IPR associated with
this interrupt and it is delivered to both Interrupt Selectors. This IPR bit is
qualified by the destination register contents for that interrupt before the
Interrupt Selector compares its priority to the priority of all other
requesting interrupts for that processor. If the interrupt is programmed to
be edge sensitive, the IPR bit is cleared when the vector for that interrupt
is returned when the Interrupt Acknowledge register is examined. On the
other hand, if the interrupt is a direct/multicast class interrupt, there are two
bits in the IPR associated with this interrupt. One bit for each processor.
there are two types of inputs to the Interrupt Selectors. If the interrupt is a
distributed class interrupt, there is a single bit in the IPR associated with
this interrupt and it is delivered to both Interrupt Selectors. This IPR bit is
qualified by the destination register contents for that interrupt before the
Interrupt Selector compares its priority to the priority of all other
requesting interrupts for that processor. If the interrupt is programmed to
be edge sensitive, the IPR bit is cleared when the vector for that interrupt
is returned when the Interrupt Acknowledge register is examined. On the
other hand, if the interrupt is a direct/multicast class interrupt, there are two
bits in the IPR associated with this interrupt. One bit for each processor.