Motorola MVME5100 用户手册

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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

NIRQ

NUMBER OF IRQs. The number of the highest external
IRQ source supported. The IPI, Timer, and PHB Detected
Error interrupts are excluded from this count.

NCPU

NUMBER OF CPUs. The number of the highest physical
CPU supported. There are two CPUs supported by this
design. CPU #0 and CPU #1.

VID

VERSION ID. Version ID for this interrupt controller.
This value reports what level of the specification is
supported by this implementation. Version level of 02 is
used for the initial release of the MPIC specification.

Global Configuration Register

RESET RESET

CONTROLLER. Writing a one to this bit forces

the controller logic to be reset. This bit is cleared
automatically when the reset sequence is complete. While
this bit is set, the values of all other register are undefined.

EINTT

External Interrupt Type. This read only bit indicates the
external interrupt type: serial or parallel mode. When this
bit is set MPIC is in serial mode for external interrupts 0
through 15. When this bit is cleared MPIC is in parallel
mode for external interrupts.

Offset

$01020

Bit

3
1

3
0

2
9

2
8

2
7

2
6

2
5

2
4

2
3

2
2

2
1

2
0

1
9

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0 9 8 7 6 5 4 3 2 1 0

Name

GLOBAL CONFIGURATION

RESET

EINTT

TIE

Operation

R/W

Reset

$00