Motorola MVME5100 用户手册
2-120
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
Timer Basecount Registers
CI
COUNT INHIBIT. Setting this bit to one inhibits
counting for this timer. Setting this bit to zero allows
counting to proceed.
counting for this timer. Setting this bit to zero allows
counting to proceed.
BC
BASE COUNT. This field contains the 31 bit count for
this timer. When a value is written into this register and
the CI bit transitions from a 1 to a 0, it is copied into the
corresponding Current Count register and the toggle bit in
the Current Count register is cleared. When the timer
counts down to zero, the Current Count register is
reloaded from the Base Count register and the timer’s
interrupt becomes pending in MPIC processing.
this timer. When a value is written into this register and
the CI bit transitions from a 1 to a 0, it is copied into the
corresponding Current Count register and the toggle bit in
the Current Count register is cleared. When the timer
counts down to zero, the Current Count register is
reloaded from the Base Count register and the timer’s
interrupt becomes pending in MPIC processing.
Offset
Timer 0 - $01110
Timer 1 - $01150
Timer 2 - $01190
Timer 1 - $01150
Timer 2 - $01190
Timer 3 - $011D0
Bit
3
1
1
3
0
0
2
9
9
2
8
8
2
7
7
2
6
6
2
5
5
2
4
4
2
3
3
2
2
2
2
1
1
2
0
0
1
9
9
1
8
8
1
7
7
1
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
0 9 8 7 6 5 4 3 2 1 0
0 9 8 7 6 5 4 3 2 1 0
Name
TIMER BASECOUNT
CI
BC
Operation
R/
W
W
R/W
Reset
1
$00000000