Motorola MVME5100 用户手册
Functional Description
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Notes
1. No opportunity for error since no read of SDRAM occurs
during a four-beat write.
during a four-beat write.
2. The SMC asserts Hawk’s internal error interrupt output upon
detecting an interrupt-qualified error condition. The potential
sources of Hawk’s internal error interrupt assertion are single-bit
error, multiple-bit error, and single-bit error counter overflow.
detecting an interrupt-qualified error condition. The potential
sources of Hawk’s internal error interrupt assertion are single-bit
error, multiple-bit error, and single-bit error counter overflow.
Error Logging
ECC error logging is facilitated by the SMC because of its internal latches.
When an error (single- or double-bit) occurs, the SMC records the address
and syndrome bits associated with the data in error. Once the error logger
has logged an error, it does not log any more until the elog control /status
bit has been cleared by software, unless the currently logged error is
single-bit and a new, double-bit error is encountered. The logging of errors
that occur during scrub can be enabled/disabled in software. Refer to the
When an error (single- or double-bit) occurs, the SMC records the address
and syndrome bits associated with the data in error. Once the error logger
has logged an error, it does not log any more until the elog control /status
bit has been cleared by software, unless the currently logged error is
single-bit and a new, double-bit error is encountered. The logging of errors
that occur during scrub can be enabled/disabled in software. Refer to the
section in this chapter for more information.