Motorola MVME5100 用户手册
3-26
Computer Group Literature Center Web Site
System Memory Controller (SMC)
3
Figure 3-6. Programming Sequence for I
2
C Random Read
READ I
2
C STATUS REG
CMPLT=1?
N
Y
LOAD “WORD ADDR x” TO
I
2
C TRANSMITTER DATA REG
READ I
2
C STATUS REG
CMPLT=ACKIN=1?
N
Y
LOAD “$09” (START CONDITION) TO
I
2
C CONTROL REG
LOAD “DEVICE ADDR+WR BIT” TO
I
2
C TRANSMITTER DATA REG
READ I
2
C STATUS REG
CMPLT=ACKIN=1?
N
Y
LOAD “$05” (STOP CONDITION) TO
I
2
C CONTROL REG
LOAD “DUMMY DATA” TO
I
2
C TRANSMITTER DATA REG
READ I
2
C STATUS REG
CMPLT=1?
N
Y
END
LOAD “$09” (REPEATED START
CONDITION) TO I
2
C CONTROL REG
LOAD “DEVICE ADDR+RD BIT” TO
I
2
C TRANSMITTER DATA REG
READ I
2
C STATUS REG
CMPLT=ACKIN=1?
N
Y
LOAD “DUMMY DATA” TO
I
2
C TRANSMITTER DATA REG
READ I
2
C STATUS REG
CMPLT=DATIN=1?
N
Y
BEGIN
READ I
2
C RECEIVER DATA REG
START
M
S
B
S
B
SDA
DEVICE ADDR
W
R
R
A
C
K
C
K
WORD ADDR x
A
C
K
C
K
START
M
S
B
S
B
DEVICE ADDR
R
D
D
A
C
K
C
K
DATA x
N
O
A
C
K
O
A
C
K
STOP
ACK and DATA from Slave Device
*
*
*
*
(*)
:
Stop condition should be generated to abort the transfer after a software wait loop (~1ms) has been expired