Motorola MVME5100 用户手册
3-46
Computer Group Literature Center Web Site
System Memory Controller (SMC)
3
ECC Control Register
refdis
When set, refdis causes the refresher and all of its
associated counters and state machines to be cleared and
maintained that way until refdis is removed (cleared). If a
refresh cycle is in process when refdis is updated by a
write to this register, the update does not take effect until
the refresh cycle has completed. This prevents the
generation of illegal cycles to the SDRAM when refdis is
updated.
associated counters and state machines to be cleared and
maintained that way until refdis is removed (cleared). If a
refresh cycle is in process when refdis is updated by a
write to this register, the update does not take effect until
the refresh cycle has completed. This prevents the
generation of illegal cycles to the SDRAM when refdis is
updated.
rwcb
rwcb, when set, causes reads and writes to SDRAM from
the PPC60x bus to access check-bit data rather than
normal data. The data path used for reading and writing
check bits is D0-D7. Each 8-bit check-bit location
services 64 bits of normal data.
the PPC60x bus to access check-bit data rather than
normal data. The data path used for reading and writing
check bits is D0-D7. Each 8-bit check-bit location
services 64 bits of normal data.
shows the
relationship between normal data and check-bit data.
Address
$FEF80028
Bit
0
1
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13
14
15
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18
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22
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28
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31
Name
0
0
0
0
0
re
fd
is
rwc
b
de
rc
rc
0
0
0
ap
ie
ie
n
sc
ie
n
dp
ie
ie
n
sien
mien
in
t
0
0
0
0
0
0
0
mb
e_m
e_m
e
Operation
R
R
R
R
R
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/C
READ ZERO
R
R
R
R
R
R
R
R/W
Reset
X
X
X
X
X
0 P
L
L
0 P
L
L
1 P
L
L
X
X
X
0P
L
L
0 P
L
L
0 P
L
L
0 P
L
L
0P
L
L
0P
L
L
X
X
X
X
X
X
X
0 P
L
L