Motorola MVME5100 用户手册
Programming Model
http://www.motorola.com/computer/literature
3-57
3
ROM B Base/Size Register
Writes to this register must be enveloped by a period of time in which no
accesses to ROM/Flash Block B, occur. A simple way to provide the
envelope is to perform at least two accesses to this (or another of the
SMC’s registers before and after the write).
accesses to ROM/Flash Block B, occur. A simple way to provide the
envelope is to perform at least two accesses to this (or another of the
SMC’s registers before and after the write).
ROM B BASE
These control bits define the base address for ROM/Flash
Block B. ROM B BASE bits 0-11 correspond to PPC60x
address bits 0 - 11 respectively. For larger ROM/Flash
sizes, the lower significant bits of ROM B BASE are
ignored. This means that the block’s base address will
always appear at an even multiple of its size. ROM B
BASE is initialized to $FF4 at power-up or local bus reset.
Block B. ROM B BASE bits 0-11 correspond to PPC60x
address bits 0 - 11 respectively. For larger ROM/Flash
sizes, the lower significant bits of ROM B BASE are
ignored. This means that the block’s base address will
always appear at an even multiple of its size. ROM B
BASE is initialized to $FF4 at power-up or local bus reset.
Note that in addition to the programmed address, the first
1Mbyte of Block B also appears at $FFF00000 -
$FFFFFFFF if the rom_b_rv bit is set.
1Mbyte of Block B also appears at $FFF00000 -
$FFFFFFFF if the rom_b_rv bit is set.
Also note that the combination of ROM_B_BASE and
rom_b_siz should never be programmed such that
ROM/Flash Block B responds at the same address as the
CSR, SDRAM, External Register Set, or any other slave
on the PowerPC bus.
rom_b_siz should never be programmed such that
ROM/Flash Block B responds at the same address as the
CSR, SDRAM, External Register Set, or any other slave
on the PowerPC bus.
Address
$FEF80058
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
ROM B BASE
rom
_b_
64
ro
m b
si
z0
z0
ro
m b
si
z1
z1
ro
m b
si
z2
z2
0
0
0
0
0
rom
_b_
rv
rom
b e
n
rom
b we
Operation
READ/WRITE
R
R/W
R/W
R/W
READ ZERO
R
R
R
R
R
R/W
R/W
R/W
Reset
$FF4 PL
V P
0 P
L
0 P
L
0 P
L
X
X
X
X
X
X
V P
0 P
L
0 P
L