Motorola MVME5100 用户手册
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Product Data and Memory Maps
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connector. The SBC mode (also know as 761 mode or IPMC mode) is
backwards compatible with the MVME761 transition card and P2 adapter
card (excluding PMC IO routing) used on MVME2600/2700 models.
PMC mode is backwards compatible with the MVME2300 and
MVME2400 models. The SBC mode is accomplished by configuring
planar jumpers and attaching an IPMC761 PMC card in PMC slot 1 of the
MVME5100. Refer to the IPMC712/761 I/O Module Installation and Use
manual for additional installation and programming information. PMC
mode is accomplished by configuring planar jumpers. The P2 IO mode
jumper configuration for the SBC and PMC modes are described in the
MVME5100 Single Board Computer Installation and Use manual.
backwards compatible with the MVME761 transition card and P2 adapter
card (excluding PMC IO routing) used on MVME2600/2700 models.
PMC mode is backwards compatible with the MVME2300 and
MVME2400 models. The SBC mode is accomplished by configuring
planar jumpers and attaching an IPMC761 PMC card in PMC slot 1 of the
MVME5100. Refer to the IPMC712/761 I/O Module Installation and Use
manual for additional installation and programming information. PMC
mode is accomplished by configuring planar jumpers. The P2 IO mode
jumper configuration for the SBC and PMC modes are described in the
MVME5100 Single Board Computer Installation and Use manual.
Serial Presence Detect (SPD) Definitions
The MVME5100 SPD uses the SPD JEDEC standard definition. On-board
SPD for SDRAM Bank A or both A and B of the Hawk is accessed at
Address $A8 . Only Bank A or Banks A and B may be populated. If both
Banks A and B are populated, they will be of the same speed and memory
size. Memory Mezzanine 1 SPD for SDRAM Bank C of the Hawk is
accessed at Address $AA. Memory Mezzanine 2 SPD for SDRAM Bank
E of the Hawk is accessed at address $AC.
SPD for SDRAM Bank A or both A and B of the Hawk is accessed at
Address $A8 . Only Bank A or Banks A and B may be populated. If both
Banks A and B are populated, they will be of the same speed and memory
size. Memory Mezzanine 1 SPD for SDRAM Bank C of the Hawk is
accessed at Address $AA. Memory Mezzanine 2 SPD for SDRAM Bank
E of the Hawk is accessed at address $AC.
The SPD format conforms to the JEDEC industry standard JESD21-C.
Hawk ASIC
The Hawk ASIC provides the bridge function between the MPC60x bus
and the PCI local bus. It provides 32-bit addressing and 64-bit data. The
64-bit addressing capability (dual address cycle) is not supported. The
Hawk supports various PowerPC processor external bus frequencies, up to
100MHz.
and the PCI local bus. It provides 32-bit addressing and 64-bit data. The
64-bit addressing capability (dual address cycle) is not supported. The
Hawk supports various PowerPC processor external bus frequencies, up to
100MHz.
There are four programmable map decoders for each direction to provide
flexible address mappings between the MPC and the PCI local bus. Refer
to Chapters 2 and 3 in this manual for more programming information on
the Hawk.
flexible address mappings between the MPC and the PCI local bus. Refer
to Chapters 2 and 3 in this manual for more programming information on
the Hawk.