Motorola MVME5100 用户手册

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Product Data and Memory Maps

The MVME5100’s NVRAM/RTC and Watchdog Timer functions are 
supplied by an M48T37V device and is fully compliant with the 
PowerPlusII internal programming configuration. The M48T37V provides 
32K of non-volatile SRAM, a time-of-day clock, and a watchdog timer. 
Accesses to the M48T37V is accomplished via three registers: the 
NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC Address 
Strobe 1 Register, and the NVRAM/RTC Data Port Register. The 
NVRAM/RTC Address Strobe 0 Register latches the lower 8 bits of the 
address and the NVRAM/RTC Address Strobe 1 Register latches the upper 
5 bits of the address

The NVRAM and RTC is accessed through the above three registers. 
When accessing an NVRAM/RTC location, perform the following 
procedure:

1. Write the low address (A7-A0) of the NVRAM to the 

NVRAM/RTC STB0 register,

2. Write the high address (A15-A8) of the NVRAM to the 

NVRAM/RTC STB1 register, and

3. Then read or write the NVRAM/RTC Data Port.

The M48T37V RST_L output (pin 2) is connected to the board 
reset logic. If the Watchdog Timer is programmed to generate a 
reset, a board reset will occur when this output is activated.

Refer to the M48T37V Data Sheet for additional details and programming 
information.

80C8

NVRAM/RTC Address Strobe 0 (A7-A0)

80D0

NVRAM/RTC Address Strobe 1 (A15-A8)

80D8

NVRAM/RTC Data Register