Motorola MVME5100 用户手册
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Product Data and Memory Maps
1
IPMC7xx ISA Bus Resources
The following subsections provide resource information pertaining to ISA
bus resources that are present, if an IPMC712 or IPMC761 is mounted on
the MVME5x00 Series Computer. They are accessible through the
W83C554 PIB, which is present on the IPMC module.
bus resources that are present, if an IPMC712 or IPMC761 is mounted on
the MVME5x00 Series Computer. They are accessible through the
W83C554 PIB, which is present on the IPMC module.
W83C554 PIB Registers
The PIB contains ISA Bridge I/O registers for various functions. These
registers are actually accessible from the PCI bus. Refer to the W83C554
Data Book for details.
registers are actually accessible from the PCI bus. Refer to the W83C554
Data Book for details.
PC87308VUL Super I/O (ISASIO) Strapping
The PC87308VUL Super I/O (ISASIO) provides the following functions
to the MVME5100 series: a keyboard interface, a PS/2 mouse interface, a
PS/2 floppy port, two async serial ports and a parallel port. Refer to the
PC87308VUL Data Sheet for additional details and programming
information.
to the MVME5100 series: a keyboard interface, a PS/2 mouse interface, a
PS/2 floppy port, two async serial ports and a parallel port. Refer to the
PC87308VUL Data Sheet for additional details and programming
information.
The following table shows the hardware strapping for the Super I/O
device:
device:
Table 1-18. Strap Pins Configuration for the PC87308VUL
Pins
Reset Configuration
CFG0
0 - FDC, KBC and RTC wake up inactive.
CFG1
1 - Xbus Data Buffer (XDB) enabled.
CFG3, CFG2
00 - Clock source is 24MHz fed via X1 pin.
BADDR1, BADDR2
11 - PnP Motherboard, Wake in Config State. Index $002E.
SELCS
1 - CS0# on CS0# pin.