Motorola MVME5100 用户手册
Functional Description
http://www.motorola.com/computer/literature
2-13
2
Upon completion of a prefetched read transaction, any residual read data
left within the PCI FIFO will be invalidated (discarded). The PHB does not
have a mechanism for snooping the PPC60x bus for transactions associated
with the prefetched read data within the PCI FIFO. Therefore, caution
should be exercised when using the prefetch option within coherent
memory space.
left within the PCI FIFO will be invalidated (discarded). The PHB does not
have a mechanism for snooping the PPC60x bus for transactions associated
with the prefetched read data within the PCI FIFO. Therefore, caution
should be exercised when using the prefetch option within coherent
memory space.
The PPC Master never performs prefetch reads beyond the address range
mapped within the PCI Slave map decoders. As an example, assume PHB
has been programmed to respond to PCI address range $10000000 through
$1001FFFF with an offset of $2000. The PPC Master performs its last read
on the PPC60x bus at cache line address $3001FFFC or word address
$3001FFF8.
mapped within the PCI Slave map decoders. As an example, assume PHB
has been programmed to respond to PCI address range $10000000 through
$1001FFFF with an offset of $2000. The PPC Master performs its last read
on the PPC60x bus at cache line address $3001FFFC or word address
$3001FFF8.
00
xx
1
Read
4 cache
lines
FIFO <= 0
cache lines
FIFO >= 4
cache lines
Read Line
xx
00
x
Read Mul-
tiple
01
xx
1
Read
4 cache
lines
FIFO <= 1
cache line
FIFO >= 4
cache lines
Read Line
xx
01
x
Read Mul-
tiple
10
xx
1
Read
4 cache
lines
FIFO <= 2
cache lines
FIFO >= 4
cache lines
Read Line
xx
10
x
Read Mul-
tiple
11
xx
1
Read
4 cache
lines
FIFO <= 3
cache lines
FIFO >= 4
cache lines
Read Line
xx
11
x
Read Mul-
tiple
Table 2-4. PPC Master Read Ahead Options (Continued)
RXFT
RMFT
RAEN
PCI
Command
Initial
Read Size
Continuation
Subsequent
Read Size