Motorola MVME5100 用户手册
Functional Description
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be subject to a time-out period. During non-PCI bound cycles, the PPC
Timer aborts the timing of the transaction any time it detects XTOCLM_
has been asserted.
Timer aborts the timing of the transaction any time it detects XTOCLM_
has been asserted.
PCI Bus Interface
The PCI Interface of the PHB is designed to connect directly to a PCI
Local Bus and supports Master and Target transactions within Memory
Space, I/O Space, and Configuration Space.
Local Bus and supports Master and Target transactions within Memory
Space, I/O Space, and Configuration Space.
PCI Address Mapping
The PHB provides three resources to the PCI:
❏
Configuration registers mapped into PCI Configuration space
❏
PPC bus address space mapped into PCI Memory space
❏
MPIC control registers mapped into either PCI I/O space or PCI
Memory space
Memory space
Configuration Registers
The PHB Configuration registers are mapped within PCI Configuration
space according to how the system connects Hawk’s DEVSEL_ pin. The
PHB provides a configuration space that is fully compliant with the PCI
Local Bus Specification 2.1 definition for configuration space. There are
two base registers within the standard 64 byte header that are used to
control the mapping of MPIC. One register is dedicated to mapping MPIC
into PCI I/O space, and the other register is dedicated to mapping MPIC
into PCI Memory space. The mapping of PPC address space is handled by
device specific registers located above the 64 byte header. These control
registers support a mapping scheme that is functionally similar to the PCI-
to-PPC mapping scheme described in the section titled PPC Address
Mapping.
space according to how the system connects Hawk’s DEVSEL_ pin. The
PHB provides a configuration space that is fully compliant with the PCI
Local Bus Specification 2.1 definition for configuration space. There are
two base registers within the standard 64 byte header that are used to
control the mapping of MPIC. One register is dedicated to mapping MPIC
into PCI I/O space, and the other register is dedicated to mapping MPIC
into PCI Memory space. The mapping of PPC address space is handled by
device specific registers located above the 64 byte header. These control
registers support a mapping scheme that is functionally similar to the PCI-
to-PPC mapping scheme described in the section titled PPC Address
Mapping.