Clevo M730T 用户手册
Schematic Diagrams
B - 40 Power Sequence Diagram
B.Schematic Diagrams
Power Sequence Diagram
14
13
C L_ PW RO K
6
3 .3 VM
DD _O N
SL P_ M#
DR AM V R
10
7
M ULT I I/ O BO AR D
CL _P WR OK
9
5VS
6
FO R ME
IC S9 LP R3 63E GL F
Other
1
S C4 72 B
Other
V R
PCI
9
Platform
1. 5V S_ PW RGD
4 a
Processor
SC 41 1
5b
2
1 50 m s
6
5 b
1 5
12
8
DE LAY
P LT _R ST #
1. 5V S
FOR M E
6
3
S C4 86
1 2- 1
3.3 VS
DD _ON
3
MOS FE T
1.0 5V S
CL KE N#
H_P WR GD
Penryn
4 b
6
PW R_ SW #
C lo ck G en era to r
1 .0 5V M
Cantiga
DE LA Y_ PW RGD
D EL AY
Devices
5 b
CLK _P WR GD
3
CL _P WR OK
PM _R SM RS T#
CL _P WRO K
GFX VR
NORTH BRIDGE
13
6
PCI _R ST #
V GF X_ CO RE
PW R_ BT N#
G FX _V RE N
LT C3 85 0
I TE 85 12 E
5 V
5 a
DE LA Y_ PW RG D
A PL 59 13
SU SC #
11
M OS FE T
EC
V RM _P WR GD
1 .8 V
1 7
1. 8V _P WR GD
S B_ PW RO K
VC OR E_ ON
1. 05 VM _P WR GD
1 6
0 .9 VS M
3 .3 V
9
SC 45 2
SOUTH BRIDGE
Devices
VC OR E
M720T V0.0 BOOT BLOCK DIAGRAM
V DD 3/ VD D5
75 ms
9
H _C PU RS T#
ICH9-M
? ? ? ? ? ?
SU SB #
VCORE VR
S US B#
1 6
6
C L_ PW RO K
Sheet 39 of 40
Power Sequence
Diagram