Motorola MC68340 用户手册
MOTOROLA
MC68340 USER’S MANUAL
8- 15
COUNTER
CLOCK
TGATE
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COUNTER
TG BIT SET
TIMEOUT
TO BIT SET
ENABLE
MODEx Bits in Control Register = 110
TGE Bit of the Control Register = 1
TGE Bit of the Control Register = 1
0
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Figure 8-10. Event Count Mode
The timer is enabled by setting the SWR and CPE bits in the CR and, if
TGATE
≈
is
enabled (TGE bit of the CR is set), then asserting
TGATE
≈
. When the timer is enabled,
the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded
with the value of $FFFF. With each successive falling edge of the counter clock, the
counter decrements. The PREL1 and PREL2 registers are not used in this mode.
with the value of $FFFF. With each successive falling edge of the counter clock, the
counter decrements. The PREL1 and PREL2 registers are not used in this mode.
If
TGATE
≈
is not enabled (CR TGE bit is cleared), then
TGATE
≈
does not start or stop
the timer or affect the TG bit of the SR. In this case, the counter would begin counting on
the falling edge of the counter clock immediately after the SWR and CPE bits in the CR
are set.
the falling edge of the counter clock immediately after the SWR and CPE bits in the CR
are set.
If
TGATE
≈
is enabled (CR TGE bit is set), then the assertion of
TGATE
≈
starts the
counter. The negation of
TGATE
≈
disables the counter, sets the SR TG bit, and clears the
ON bit in the SR. If
TGATE
≈
is reasserted, the timer resumes counting from where it was
stopped, and the ON bit is set again. Further assertions and negations of
TGATE
≈
have
the same effect. The TGL bit in the SR reflects the level of
TGATE
≈
at all times.
If the counter counts down to the value stored in the COM register, the COM and TC bits
in the SR are set. If the counter counts down to $0000, a timeout is detected. This event
sets the TO in the SR and clears the COM bit. At timeout, the next falling edge of the
counter clock reloads the counter with $FFFF. TOUTx transitions at timeout or is disabled
as programmed by the CR OC bits. The SR OUT bit reflects the level on TOUTx.
in the SR are set. If the counter counts down to $0000, a timeout is detected. This event
sets the TO in the SR and clears the COM bit. At timeout, the next falling edge of the
counter clock reloads the counter with $FFFF. TOUTx transitions at timeout or is disabled
as programmed by the CR OC bits. The SR OUT bit reflects the level on TOUTx.
To determine the number of cycles counted, the value in the CNTR must be read,
inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count
of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater
duration, the value in the POx bits in the SR are readable and can be thought of as an
extension of the least significant bits in the CNTR.
inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count
of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater
duration, the value in the POx bits in the SR are readable and can be thought of as an
extension of the least significant bits in the CNTR.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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