Texas Instruments TMS320C6747 DSP 用户手册
2
Architecture
2.1
USB1 Module Clock and Reset
2.1.1
Internal System Bus Clocks Needed by the USB1 Module
2.1.2
USB1 Module Local Bus Clock and Local Reset
2.1.3
USB1 Module Bus 48-MHz Reference Clock
Architecture
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The USB1 module requires that several different clocks are present before it can be accessed:
1. Internal system bus clocks for accesses by the ARM or DSP (Device SYSCLK2 and SYSCLK4)
2. Local bus clock to the USB Host controller (derived from SYSCLK4)
3. USB bus side 48-MHz reference clock must be present. Several options are available to source this
2. Local bus clock to the USB Host controller (derived from SYSCLK4)
3. USB bus side 48-MHz reference clock must be present. Several options are available to source this
clock.
The internal system bus clocks SYSCLK2 and SYSCLK4 are normally configured during the device reset
process; as the device PLL controller is initialized. The USB host controller operates in the SYSCLK4
domain but SYSCLK2 since most of the device level bus infrastructure operates on the SYSCLK2 domain.
Normally one or both of the host CPU clock domains (SYSCLK6 for the ARM and SYSCLK1 for the DSP)
will be enabled as well.
process; as the device PLL controller is initialized. The USB host controller operates in the SYSCLK4
domain but SYSCLK2 since most of the device level bus infrastructure operates on the SYSCLK2 domain.
Normally one or both of the host CPU clock domains (SYSCLK6 for the ARM and SYSCLK1 for the DSP)
will be enabled as well.
The USB Host Controller actually operates from a local (gated) version of SYSCLK4. This allows the
module be put into a low power state when not in use. The module also has its own local reset that is
asserted during a device level reset and remains asserted until released by software. Additionally software
can at any time assert a hardware reset on the USB Host Controller individually, causing it to reinitialize
without affecting any of the other peripherals on the device.
module be put into a low power state when not in use. The module also has its own local reset that is
asserted during a device level reset and remains asserted until released by software. Additionally software
can at any time assert a hardware reset on the USB Host Controller individually, causing it to reinitialize
without affecting any of the other peripherals on the device.
Both the local clock and local reset of the USB Host Controller are under the control of the device level
Power Sleep Controller 1 (PSC1) module. This module controls many local power sleep controller
modules, and local power sleep controller 2 (LPSC2) of PSC1 controls the USB OHCI Host Controller.
Power Sleep Controller 1 (PSC1) module. This module controls many local power sleep controller
modules, and local power sleep controller 2 (LPSC2) of PSC1 controls the USB OHCI Host Controller.
This device includes an integrated USB 1.1 Phy for the OHCI Host Controller's Root Hub (Port 0). This
Phy requires a 48-MHz reference clock for proper operation. Two options are available to provide this
reference clock:
Phy requires a 48-MHz reference clock for proper operation. Two options are available to provide this
reference clock:
•
Use the reference clock generated by the USB0 module integrated high-speed phy. The high-speed
phy includes a phase locked loop (PLL) that is capable of generating a 48-MHz reference clock from
multiple different input clock options. This method is probably the most convenient as it does not
require an externally sourced clock, and the PLL in the USB0 module has flexibility in the frequency of
its input clock. However when using this option, the USB0 phy must be operating in order to use the
USB1 OHCI host controller. (This does not mean that the USB0 module must be running, only that its
phy needs to be configured properly and enabled).
phy includes a phase locked loop (PLL) that is capable of generating a 48-MHz reference clock from
multiple different input clock options. This method is probably the most convenient as it does not
require an externally sourced clock, and the PLL in the USB0 module has flexibility in the frequency of
its input clock. However when using this option, the USB0 phy must be operating in order to use the
USB1 OHCI host controller. (This does not mean that the USB0 module must be running, only that its
phy needs to be configured properly and enabled).
•
Provide the 48 MHz clock externally, on the USB_REFCLKIN pin.
For details on device level configuration of the 48-MHz reference clock, see the device clocking chapter in
the TMS320C6745/C6747 DSP System Reference Guide (
the TMS320C6745/C6747 DSP System Reference Guide (
).
The USB host controller completes its reset after the host controller clock is transitioned from disabled to
enabled and the host controller reset is removed. After system software turns on the clock to the USB host
controller and removes it from reset, it is necessary to wait until the USB host controller internal reset
completes. To ensure that the USB host controller has completely reset, system software must wait until
reads of both the HCREVISION register and the HCHCCA register return their correct reset default
values.
enabled and the host controller reset is removed. After system software turns on the clock to the USB host
controller and removes it from reset, it is necessary to wait until the USB host controller internal reset
completes. To ensure that the USB host controller has completely reset, system software must wait until
reads of both the HCREVISION register and the HCHCCA register return their correct reset default
values.
Universal Serial Bus OHCI Host Controller
8
SPRUFM8 – September 2008