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UM10301_1 

© NXP B.V. 2008. All rights reserved.

The tuning fork crystal’s drive level is extremely low (< 1 μW) and the input of the 
amplifier used in the oscillator (pin OSCI) has a very high impedance. This makes the 
circuit susceptible to signals generated by other circuits on the board, or further away. 
Generally the lower the timekeeping current, the more susceptible the crystal 
connections will be to noise, since lower current consumption implies higher impedance 
nodes. The track from crystal to amplifier input can easily work as an antenna and 
therefore should be kept as short as possible. The output of the amplifier OSCO is 
connected to the other side of the crystal and is thus a sensitive node as well. In order to 
ensure proper operation some PCB guidelines should be strictly adhered to. 

 

•  Traces between the oscillator input and output pins, the crystal and the external load 

capacitors, should be as short as possible. Place also a 100 nF – 470 nF decoupling 
capacitor close to the RTC with short tracks to V

DD

 and V

SS

. 

•  The external load capacitor’s layout preferably is symmetrical and both ground 

connections should be as close as possible. 

•  In order to avoid direct signal coupling, OSCI and OSCO traces should be routed as 

far away as possible from each other. 

•  Routing on inner layers and vias of the oscillator signals must be avoided. Vias form 

an inductance. 

•  Digital signal lines should be kept as far as possible from the crystal (this includes 

the serial bus signals to the RTC). 

•  Digital signal lines or other signal lines with high frequency content should not be 

routed on inner layers under the crystal / RTC area. 

•  Route the CLKOUT signal away from the crystal connections. If possible route a 

ground or power track between the CLKOUT signal and crystal connections. 

•  The crystal housing (metal-can packages) should be connected to ground (not for the 

PCF8573, PCF8583 and PCF8593; here connect the housing to V

DD

). 

•  The PCA8565A and PCF2123 (here for C

L

 = 7 pF) include two integrated oscillator 

capacitors and thus don’t need external oscillator capacitances. This also means that 
no compensation can be made by choosing slightly smaller values if the layout 
introduces parasitic capacitance due to ground signals or planes.  

•  A dedicated RTC ground plane should be placed beneath the crystal and the 

input/output capacitors, possibly also running beneath the RTC itself. Input/output 
capacitors can be connected to this ground plane. This ground plane should be 
connected with a short trace to V

SS

 of the real-time clock, and should not be 

connected to any other ground signals. Therefore only one connection between this 
ground plane and general GND exists and thus it is ensured that no unknown 
currents will run via the dedicated RTC ground plane. Remember that success in 
noise/disturbance-free design depends on always knowing where all the currents 
flow (and keeping them away from where they are not wanted). 

A layout proposal using leaded components is shown in Fig 14. In this example the 
external oscillator capacitor is adjustable. Often a fixed capacitor wil be used. In this case 
place it horizontally such that the loop from the RTC via the capacitor to GND is as small 
as possible. See also Fig 15 which shows a layout example with SMDs.