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UM10301_1 

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The timer counts down from a software-loaded 8-bit binary value, n. Loading the counter 
with 0 effectively stops the timer. Values from 1 to 255 are valid. When the counter 
reaches 1, the countdown Timer Flag (TF) will be set and the counter automatically re-
loads and starts the next timer period. The timer has two operating modes, TI and TP. If 
the timer interrupt is enabled, the bit TI/TP determines the operating mode. For more 
details see below. Reading the timer will return the current value of the countdown 
counter (see Fig 20). 

If a new value of n is written before the end of the current timer period, then this value will 
take immediate effect. It is not recommended (especially when using the faster time 
source clocks) to change n without first disabling the counter. The counter is disabled by 
setting Timer Enable TE = 0. The update of n is asynchronous to the timer clock, 
therefore changing it without setting TE = 0 may result in a corrupted value loaded into 
the countdown counter which results in an undetermined countdown period for the first 
period. However, the probability of this happening depends on the selected timer source 
clock. If the timer clock is not first stopped then there is a possibility that the timer clock 
and the interface clock which is loading the count down timer could arrive at the same 
time. This may corrupt the count down value. With a 1-minute clock (1/60 Hz) this is 
unlikely to happen, especially when the application software waits for the timer to trigger 
and then straight away sets a new value for n. As long as this new value is written within 
1 minute here, there is no problem. The same reasoning is valid for the other timer 
source clocks but obviously there is much less time to do so. If the 1-second clock is 
selected this would work too if the microcontroller communicating with the RTC is fast. 
For faster timer source clocks it gets unreliable and should be avoided.  

Also in the case where the timer clock and the interface clock arrive at the same time 
which may corrupt the first count down value, the countdown value n will however be 
correctly stored and correctly loaded on subsequent timer periods. 

When starting the timer for the first time, the first period will have an uncertainty which is 
a result of the enable instruction being generated from the interface clock (I

2

C or SPI) 

which is asynchronous from the timer source clock. Subsequent timer periods will have 
no such delay. Therefore only the first timer period will exhibit this uncertainty. The 
amount of delay for the first timer period will depend on the chosen source clock, see 
Table 11. 

4096 Hz 

N 

n + 1 

64 Hz 

N 

n + 1 

1 Hz 

(n-1) + 1/64 Hz 

n + 1/64 Hz 

1/60 Hz 

(n-1) + 1/64 Hz 

n + 1/64 Hz 

 

When reading the timer, the current countdown value is returned instead of the initial 
value n. For accurate read back of the countdown value, the SPI or I

2

C bus clock (SCL) 

must be operating at a frequency of at least twice the selected timer clock. Since it is not 
possible to freeze the countdown timer counter during read back, it is recommended to 
read the register twice and check for consistent results.