Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

This is a read/write accessible register. This register controls which of the 32 combined 
hardware and software interrupt requests are enabled to contribute to FIQ or IRQ.

 

This is a write only register. This register allows software to clear one or more bits in the 
Interrupt Enable register (see 

), without having to first read it.

 

This is a read/write accessible register. This register classifies each of the 32 interrupt 
requests as contributing to FIQ or IRQ.

31:0 See 

0

Neither the hardware nor software interrupt request with this 
bit number are asserted.

-

1

The hardware or software interrupt request with this bit 
number is asserted.

31:0 See 

.

When this register is read, 1s indicate interrupt requests or software 
interrupts that are enabled to contribute to FIQ or IRQ.

When this register is written, ones enable interrupt requests or 
software interrupts to contribute to FIQ or IRQ, zeroes have no 
effect. See 

 and 

below for how to disable interrupts.

0

31:0 See 

0

Writing a 0 leaves the corresponding bit in VICIntEnable 
unchanged.

-

1

Writing a 1 clears the corresponding bit in the Interrupt 
Enable register, thus disabling interrupts for this request.