Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
193 of 792
1.
How to read this chapter
The number of GPIO pins on each port is different for LPC2458 and LPC2460/68/70/78
parts. The available pins are listed in
parts. The available pins are listed in
for each part. Bits corresponding to
unavailable pins are reserved in all GPIO related registers.
2.
Basic configuration
GPIOs are configured using the following registers:
1. Power: always enabled.
2. Clocks: See
for fast GPIO ports and the PCLKSEL1 register
) for legacy GPIO ports.
3. Pins: Select GPIO pins and their modes in PINSEL0 to PINSEL10 and PINMODE0 to
PINMODE10 (
4. Wakeup: Use the INTWAKE register (
) to configure GPIO ports 0 and 2 for
wakeup if needed.
5. Interrupts: Enable GPIO interrupts in IO0/2IntEnR (
) or IO0/2IntEnF
). Interrupts are enabled in the VIC using the VICIntEnable register
).
3.
Features
3.1 Digital I/O ports
•
GPIO PORT0 and PORT1 are ports accessible via either the group of registers
providing enhanced features and accelerated port access or the legacy group of
registers. PORT2/3/4 are accessed as fast ports only.
providing enhanced features and accelerated port access or the legacy group of
registers. PORT2/3/4 are accessed as fast ports only.
•
Accelerated GPIO functions:
– GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved.
UM10237
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
Rev. 02 — 19 December 2008
User manual
Table 156. LPC2400 available port pins
Port0
Port1
Port2
Port3
Port4
Features
Fast/Legacy
selectable
selectable
Interrupt
enabled
enabled
Fast/Legacy
selectable
selectable
Fast only
Interrupt
enabled
enabled
Fast only
Fast only
LPC2458
P0[31:0]
P1[31:0]
P2[13:0]
P2[21:16]
P2[25:24]
P2[29:28]
P3[15:0]
P3[26:23]
P4[19:0]
P4[31:24]
LPC2420/60/68/70/78
P0[31:0]
P1[31:0]
P2[31:0]
P3[31:0]
P4[31:0]