Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
198 of 792
NXP Semiconductors
UM10237
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
[1]
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
6.1 GPIO port Direction register IODIR and FIODIR(IO[0/1]DIR -
0xE002 80[0/1]8 and FIO[0/1/2/3/4]DIR - 0x3FFF C0[0/2/4/6/8]0)
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
Remark: GPIO pins P0.29 and P0.30 are shared with the USB D+/
− pins and must have
the same direction. If either P0DIR bits 29 or 30 are configured LOW in the IO0DIR or
FIO0DIR registers, both, P0.29 and P0.30, are inputs. If both, P0DIR bit 29 and bit 30 are
HIGH, both, P0.29 and P0.30, are outputs.
FIO0DIR registers, both, P0.29 and P0.30, are inputs. If both, P0DIR bit 29 and bit 30 are
HIGH, both, P0.29 and P0.30, are outputs.
Legacy registers are the IO0DIR and IO1DIR while the enhanced GPIO functions are
supported via the FIO0DIR, FIO1DIR, FIO2DIR, FIO3DIR and FIO4DIR registers.
supported via the FIO0DIR, FIO1DIR, FIO2DIR, FIO3DIR and FIO4DIR registers.
Table 160. GPIO interrupt register map
Generic
Name
Name
Description
Access
Reset
value
value
PORTn Register
Address & Name
Address & Name
IntEnR
GPIO Interrupt Enable for Rising edge.
R/W
0x0
IO0IntEnR - 0xE002 8090
IO2IntEnR - 0xE002 80B0
IO2IntEnR - 0xE002 80B0
IntEnF
GPIO Interrupt Enable for Falling edge.
R/W
0x0
IO0IntEnR - 0xE002 8094
IO2IntEnR - 0xE002 80B4
IO2IntEnR - 0xE002 80B4
IntStatR
GPIO Interrupt Status for Rising edge.
RO
0x0
IO0IntStatR - 0xE002 8084
IO2IntStatR - 0xE002 80A4
IO2IntStatR - 0xE002 80A4
IntStatF
GPIO Interrupt Status for Falling edge.
RO
0x0
IO0IntStatF - 0xE002 8088
IO2IntStatF - 0xE002 80A8
IO2IntStatF - 0xE002 80A8
IntClr
GPIO Interrupt Clear.
WO
0x0
IO0IntClr - 0xE002 808C
IO2IntClr - 0xE002 80AC
IO2IntClr - 0xE002 80AC
IntStatus
GPIO overall Interrupt Status.
RO
0x00
IOIntStatus - 0xE002 8080
Table 161. GPIO port Direction register (IO0DIR - address 0xE002 8008 and IO1DIR - address
0xE002 8018) bit description
Bit
Symbol
Value Description
Reset
value
value
31:0
P0xDIR
or
P1xDIR
or
P1xDIR
0
Slow GPIO Direction PORTx control bits. Bit 0 in IOxDIR
controls pin Px.0, bit 31 IOxDIR controls pin Px.31.
controls pin Px.0, bit 31 IOxDIR controls pin Px.31.
Controlled pin is an input pin.
0x0
1
Controlled pin is an output pin.
Table 162. Fast GPIO port Direction register (FIO[0/1/2/3/4]DIR - address
0x3FFF C0[0/2/4/6/8]0) bit description
Bit
Symbol
Value Description
Reset
value
value
31:0
FP0xDIR
FP1xDIR
FP2xDIR
FP3xDIR
FP4xDIR
FP1xDIR
FP2xDIR
FP3xDIR
FP4xDIR
0
Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR
controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.
controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.
Controlled pin is input.
0x0
1
Controlled pin is output.