Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

State of the output configured GPIO pin is determined by writes into the pin’s port IOSET 
and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine 
the final output of a pin.

In the example code:

IO0DIR = 0x0000 0080 ;pin P0.7 configured as output

IO0CLR = 0x0000 0080 ;P0.7 goes LOW

IO0SET = 0x0000 0080 ;P0.7 goes HIGH

IO0CLR = 0x0000 0080 ;P0.7 goes LOW

pin P0.7 is configured as an output (write to IO0DIR register). After this, P0.7 output is set 
to low (first write to IO0CLR register). Short high pulse follows on P0.7 (write access to 
IO0SET), and the final write to IO0CLR register sets pin P0.7 back to low level.

Write access to port’s IOSET followed by write to the IOCLR register results with pins 
outputting 0s being slightly later then pins outputting 1s. There are systems that can 
tolerate this delay of a valid output, but for some applications simultaneous output of a 
binary content (mixed 0s and 1s) within a group of pins on a single GPIO port is required. 
This can be accomplished by writing to the port’s IOPIN register.

Following code will preserve existing output on PORT0 pins P0.[31:16] and P0.[7:0] and 
at the same time set P0.[15:8] to 0xA5, regardless of the previous value of pins P0.[15:8]:

IO0PIN = (IO0PIN && 0xFFFF00FF) || 0x0000A500

The same outcome can be obtained using the fast port access.

Solution 1: using 32-bit (word) accessible fast GPIO registers

FIO0MASK = 0xFFFF00FF;

FIO0PIN  = 0x0000A500;

Solution 2: using 16-bit (half-word) accessible fast GPIO registers

FIO0MASKL = 0x00FF;

FIO0PINL  = 0xA500;

Solution 3: using 8-bit (byte) accessible fast GPIO registers

FIO0PIN1  = 0xA5;