Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

The host registers module containing the registers in the software view and handling 
AHB accesses to the Ethernet block. The host registers connect to the transmit and 
receive datapath as well as the MAC.

The DMA to AHB interface. This provides an AHB master connection that allows the 
Ethernet block to access the Ethernet SRAM for reading of descriptors, writing of 
status, and reading and writing data buffers.

The Ethernet MAC and attached RMII adapter. The MAC interfaces to the off-chip 
PHY.

The transmit datapath, including:

– The transmit DMA manager which reads descriptors and data from memory and 

writes status to memory.

– The transmit retry module handling Ethernet retry and abort situations.

– The transmit flow control module which can insert Ethernet pause frames.

The receive datapath, including:

– The receive DMA manager which reads descriptors from memory and writes data 

and status to memory.

– The Ethernet MAC which detects frame types by parsing part of the frame header.

– The receive filter which can filter out certain Ethernet frames by applying different 

filtering schemes.

– The receive buffer implementing a delay for receive frames to allow the filter to 

filter out certain frames before storing them to memory.

The Ethernet block and associated device driver software offer the functionality of the 
Media Access Control (MAC) sublayer of the data link layer in the OSI reference model 
(see IEEE std 802.3). The MAC sublayer offers the service of transmitting and receiving 
frames to the next higher protocol level, the MAC client layer, typically the Logical Link 
Control sublayer. The device driver software implements the interface to the MAC client 
layer. It sets up registers in the Ethernet block, maintains descriptor arrays pointing to 
frames in memory and receives results back from the Ethernet block through interrupts. 
When a frame is transmitted, the software partially sets up the Ethernet frames by 
providing pointers to the destination address field, source address field, the length/type 
field, the MAC client data field and optionally the CRC in the frame check sequence field. 
Preferably concatenation of frame fields should be done by using the scatter/gather 
functionality of the Ethernet core to avoid unnecessary copying of data. The hardware 
adds the preamble and start frame delimiter fields and can optionally add the CRC, if 
requested by software. When a packet is received the hardware strips the preamble and 
start frame delimiter and passes the rest of the packet - the Ethernet frame - to the device 
driver, including destination address, source address, length/type field, MAC client data 
and frame check sequence (FCS).

Apart from the MAC, the Ethernet block contains receive and transmit DMA managers that 
control receive and transmit data streams between the MAC and the AHB interface. 
Frames are passed via descriptor arrays located in host memory, so that the hardware 
can process many frames without software/CPU support. Frames can consist of multiple 
fragments that are accessed with scatter/gather DMA. The DMA managers optimize 
memory bandwidth using prefetching and buffering.