Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
300 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
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Next base address update interrupt.
•
FIFO underflow interrupt.
Each of the four individual maskable interrupts is enabled or disabled by changing the
mask bits in the LCD_INT_MSK register. These interrupts are also combined into a single
overall interrupt, which is asserted if any of the individual interrupts are both asserted and
unmasked. Provision of individual outputs in addition to a combined interrupt output
enables use of either a global interrupt service routine, or modular device drivers to
handle interrupts.
mask bits in the LCD_INT_MSK register. These interrupts are also combined into a single
overall interrupt, which is asserted if any of the individual interrupts are both asserted and
unmasked. Provision of individual outputs in addition to a combined interrupt output
enables use of either a global interrupt service routine, or modular device drivers to
handle interrupts.
The status of the individual interrupt sources can be read from the LCD_INTRAW register.
6.11.1 Master bus error interrupt
The master bus error interrupt is asserted when an ERROR response is received by the
master interface during a transaction with a slave. When such an error is encountered, the
master interface enters an error state and remains in this state until clearance of the error
has been signaled to it. When the respective interrupt service routine is complete, the
master bus error interrupt may be cleared by writing a 1 to the BERIC bit in the
LCD_INTCLR register. This action releases the master interface from its ERROR state to
the start of FRAME state, and enables fresh frame of data display to be initiated.
master interface during a transaction with a slave. When such an error is encountered, the
master interface enters an error state and remains in this state until clearance of the error
has been signaled to it. When the respective interrupt service routine is complete, the
master bus error interrupt may be cleared by writing a 1 to the BERIC bit in the
LCD_INTCLR register. This action releases the master interface from its ERROR state to
the start of FRAME state, and enables fresh frame of data display to be initiated.
6.11.2 Vertical compare interrupt
The vertical compare interrupt asserts when one of four vertical display regions, selected
using the LCD_CTRL register, is reached. The interrupt can be made to occur at the start
of:
using the LCD_CTRL register, is reached. The interrupt can be made to occur at the start
of:
•
Vertical synchronization.
•
Back porch.
•
Active video.
•
Front porch.
The interrupt may be cleared by writing a 1 to the VcompIC bit in the LCD_INTCLR
register.
register.
6.11.2.1
Next base address update interrupt
The LCD next base address update interrupt asserts when either the LCDUPBASE or
LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR
incrementers respectively. This signals to the system that it is safe to update the
LCDUPBASE or the LCDLPBASE registers with new frame base addresses if required.
LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR
incrementers respectively. This signals to the system that it is safe to update the
LCDUPBASE or the LCDLPBASE registers with new frame base addresses if required.
The interrupt can be cleared by writing a 1 to the LNBUIC bit in the LCD_INTCLR register
6.11.2.2
FIFO underflow interrupt
The FIFO underflow interrupt asserts when internal data is requested from an empty DMA
FIFO. Internally, upper and lower panel DMA FIFO underflow interrupt signals are
generated.
FIFO. Internally, upper and lower panel DMA FIFO underflow interrupt signals are
generated.
The interrupt can be cleared by writing a 1 to the FUFIC bit in the LCD_INTCLR register.