Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

 

(1) Signal polarities may vary for some displays.

LCD_TIMV (VSW)

LCDDCLK 

(panel clock)

LCD_TIMV (VBP)

 LCD_TIMV(LPP) 

LCD_TIMV (VFP)

LCDFP

(vertical synch

pulse)

back porch

(defined in line clocks)

 front porch

(defined in line clocks)

pixel data

and horizontal

controls for one

frame

one frame

all horizontal lines for one frame

see horizontal timing for STN displays

panel data clock active

(1) The active data lines will vary with the type of TFT panel.

(2) The LCD panel clock is selected and scaled by the LCD controler and used to produce LCDCLK.

(3) The duration of the LCDLP is controlled by the HSW field in the LCD_TIMH register.

(4) The polarity of the LCDLP signal is determined by the IHS bit in the LCD_POL regster.

pixel clock

(internal)

LCD_TIMH (HSW)

LCDLP 

(lhorizontal 

synch pulse)

LCD_TIMH (HBP)

LCD_TIMH(PPL) LCD_TIMH 

(HFP)

LCDDCLK

(panel clock)

horizontal back porch

(defined in pixel clocks)

horizontal front porch

(defined in pixel clocks)

one horizontal line of LCD data

LCDVD[23:0]

(panel data)

one horizontal line