Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
35 of 792
NXP Semiconductors
UM10237
Chapter 3: LPC24XX System control
3.3 Other system controls and status flags
Some aspects of controlling LPC2400 operation that do not fit into peripheral or other
registers are grouped here.
registers are grouped here.
3.3.1 System Controls and Status register (SCS - 0xE01F C1A0)
Table 28.
Reset Source Identification register (RSID - address 0xE01F C180) bit description
Bit
Symbol Description
Reset
value
value
0
POR
Assertion of the POR signal sets this bit, and clears all of the other bits in
this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
See text
1
EXTR
Assertion of the RESET signal sets this bit. This bit is cleared by POR,
but is not affected by WDT or BOD reset.
but is not affected by WDT or BOD reset.
See text
2
WDTR
This bit is set when the Watchdog Timer times out and the WDTRESET
bit in the Watchdog Mode Register is 1. It is cleared by any of the other
sources of Reset.
bit in the Watchdog Mode Register is 1. It is cleared by any of the other
sources of Reset.
See text
3
BODR
This bit is set when the 3.3 V power reaches a level below 2.6 V.
If the V
DD
voltage dips from 3.3 V to 2.5 V and backs up, the BODR bit
will be set to 1.
If the V
DD(3V3)
voltage dips from 3.3 V to 2.5 V and continues to decline
to the level at which POR is asserted (nominally 1 V), the BODR bit is
cleared.
cleared.
if the V
DD(3V3)
voltage rises continuously from below 1 V to a level above
2.6 V, the BODR will be set to 1.
This bit is not affected by External Reset nor Watchdog Reset.
Note: Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the V
indicates if the V
DD(3V3)
voltage was below 2.6 V or not.
See text
7:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
value read from a reserved bit is not defined.
NA
Table 29.
System Controls and Status register (SCS - address 0xE01F C1A0) bit description
Bit
Symbol
Value Description
Access Reset
value
0
GPIOM
GPIO access mode selection.
R/W
0
0
GPIO ports 0 and 1 are accessed via APB addresses in a fashion
compatible with previous LPC2000 devices.
compatible with previous LPC2000 devices.
1
High speed GPIO is enabled on ports 0 and 1, accessed via addresses in
the on-chip memory range. This mode includes the port masking feature
described in the GPIO chapter.
the on-chip memory range. This mode includes the port masking feature
described in the GPIO chapter.
1
EMC Reset
Disable
Disable
External Memory Controller Reset Disable.
R/W
0
0
Both EMC resets are asserted when any type of reset event occurs. In this
mode, all registers and functions of the EMC are initialized upon any reset
condition.
mode, all registers and functions of the EMC are initialized upon any reset
condition.
1
Many portions of the EMC are only reset by a power-on or brown-out event,
in order to allow the EMC to retain its state through a warm reset (external
reset or watchdog reset). If the EMC is configured correctly, auto-refresh can
be maintained through a warm reset.
in order to allow the EMC to retain its state through a warm reset (external
reset or watchdog reset). If the EMC is configured correctly, auto-refresh can
be maintained through a warm reset.