Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt 
register. Writing zero has no effect. USBSysErrIntSet is a write only register.

 

This section describes how an interrupt event on any of the endpoints is routed to the 
Vectored Interrupt Controller (VIC). For a diagram showing interrupt event handling, see 

All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an 
interrupt when they receive a packet without an error. All non-isochronous IN endpoints 
generate an interrupt when a packet has been succesfully transmitted or when a NAK 
signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see 

. For isochronous endpoints, a frame interrupt is generated every 1 ms.

The interrupt handling is different for Slave and DMA mode.

If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the 
USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For 
non-isochronous endpoints, all endpoint interrupt events are divided into two types by the 
corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint 
interrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in 
the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the 
EP_SLOW bit in USBDevIntSt. 

For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms.

The USBDevIntSt register holds the status of all endpoint interrupt events as well as the 
status of various other interrupts (see 

). By default, all interrupts (if 

enabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt 

31:0

EPxx

Clear endpoint xx (2 

≤

 

xx 

≤

 

31) System Error Interrupt request.

0

0

No effect.

1

Clear the EPxx System Error Interrupt request in the 
USBSysErrIntSt register.

31:0

EPxx

Set endpoint xx (2 

≤

 

xx 

≤

 

31) System Error Interrupt request. 0

0

No effect.

1

Set the EPxx System Error Interrupt request in the 
USBSysErrIntSt register.