Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
369 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
11.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1
byte)
Commands 0x40 to 0x5F are identical to their Select Endpoint equivalents, with the
following differences:
following differences:
•
They clear the bit corresponding to the endpoint in the USBEpIntSt register.
•
In case of a control OUT endpoint, they clear the STP and PO bits in the
corresponding Select Endpoint Register.
corresponding Select Endpoint Register.
•
Reading one byte is obligatory.
Remark: This command may be invoked by using the USBCmdCode and USBCmdData
registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the
USBEpIntClr register is recommended.
registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the
USBEpIntClr register is recommended.
11.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte
(optional))
The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical
endpoint number in hex. Not all bits can be set for all types of endpoints.
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical
endpoint number in hex. Not all bits can be set for all types of endpoints.
6
B_2_FULL
The buffer 2 status.
0
0
Buffer 2 is empty.
1
Buffer 2 is full.
7
-
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA
Table 354. Select Endpoint Register bit description
Bit
Symbol
Value Description
Reset
value
value
Table 355. Set Endpoint Status Register bit description
Bit
Symbol
Value
Description
Reset
value
value
0
ST
Stalled endpoint bit. A Stalled control endpoint is automatically
unstalled when it receives a SETUP token, regardless of the
content of the packet. If the endpoint should stay in its stalled
state, the CPU can stall it again by setting this bit. When a stalled
endpoint is unstalled - either by the Set Endpoint Status
command or by receiving a SETUP token - it is also re-initialized.
This flushes the buffer: in case of an OUT buffer it waits for a
DATA 0 PID; in case of an IN buffer it writes a DATA 0 PID. There
is no change of the interrupt status of the endpoint. When
already unstalled, writing a zero to this bit initializes the endpoint.
When an endpoint is stalled by the Set Endpoint Status
command, it is also re-initialized.
unstalled when it receives a SETUP token, regardless of the
content of the packet. If the endpoint should stay in its stalled
state, the CPU can stall it again by setting this bit. When a stalled
endpoint is unstalled - either by the Set Endpoint Status
command or by receiving a SETUP token - it is also re-initialized.
This flushes the buffer: in case of an OUT buffer it waits for a
DATA 0 PID; in case of an IN buffer it writes a DATA 0 PID. There
is no change of the interrupt status of the endpoint. When
already unstalled, writing a zero to this bit initializes the endpoint.
When an endpoint is stalled by the Set Endpoint Status
command, it is also re-initialized.
0
0
The endpoint is unstalled.
1
The endpoint is stalled.
4:1
-
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA