Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

The USB controller is configured using the following registers:

1. Power: In the PCONP register (

), set bit PCUSB.

Remark: On reset, the USB block is disabled (PCUSB = 0).

2. Clock: see 

.

3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to 

PINMODE5 (

4. Wakeup: Use the INTWAKE register (

) to enable activity on the USB bus 

port to wakeup the microcontroller from Power-down mode (see 

). 

5. Interrupts: See 

. Interrupts are enabled in the VIC using the 

VICIntEnable register (

).

6. Initialization: see 

.

This chapter describes the OTG and I

2

C portions of the USB 2.0 OTG dual role device 

controller which integrates the (OHCI) host controller, device controller, and I

2

C. The I

2

C 

interface (Master only) controls an external OTG transceiver.

USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the 
capability of existing mobile devices and USB peripherals by adding host functionality for 
connection to USB peripherals. The specification and more information on USB OTG can 
be found on the USB Implementers Forum web site.

Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 
1.0a.

Hardware support for Host Negotiation Protocol (HNP).

Includes a programmable timer required for HNP and SRP.

Supports any OTG transceiver compliant with the OTG Transceiver Specification 
(CEA-2011), Rev. 1.0.

The architecture of the USB OTG controller is shown below in the block diagram.

The host, device, OTG, and I2C controllers can be programmed through the register 
interface. The OTG controller enables dynamic switching between host and device roles 
through the HNP protocol. One port may be connected to an external OTG transceiver to