Nxp Semiconductors UM10237 用户手册

UM10237_2

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This register is the top byte of the receive FIFO. The receive FIFO is 4 bytes deep. The Rx 
FIFO is flushed by a hard reset or by a soft reset (I2C_CTL bit 7). Reading an empty FIFO 
gives unpredictable data results.

 

This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.

The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure 
occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored.

I2C_TX must be written for both write and read operations to transfer each byte. Bits [7:0] 
are ignored for master-receive operations. The master-receiver must write a dummy byte 
to the TX FIFO for each byte it expects to receive in the RX FIFO. When the STOP bit is 
set or the START bit is set to cause a RESTART condition on a byte written to the TX 
FIFO (master-receiver), then the byte read from the slave is not acknowledged. That is, 
the last byte of a master-receive operation is not acknowledged.

 

The I2C_STS register provides status information on the TX and RX blocks as well as the 
current state of the external buses. Individual bits are enabled as interrupts by the 
I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt.

4

AHB_CLK_ON

AHB master clock status.

0

0

AHB clock is not available.

1

AHB clock is available.

31:5

-

NA

Reserved, user software should not write ones 
to reserved bits. The value read from a 
reserved bit is not defined.

NA

7:0

RX Data

Receive data.

-

7:0

TX Data

Transmit data.

-

8

START

When 1, issue a START condition before transmitting this byte.

-

9

STOP

When 1, issue a STOP condition after transmitting this byte.

-

31:10 -

Reserved. User software should not write ones to reserved bits. The 
value read from a reserved bit is not defined.

-