Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
426 of 792
NXP Semiconductors
UM10237
Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter
16.4.1 UARTn Receiver Buffer Register (U0RBR - 0xE000 C000, U2RBR -
0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only)
The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR.
The UnRBR is always Read Only.
The UnRBR is always Read Only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the UnRBR.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the UnRBR.
4.2 UARTn Transmit Holding Register (U0THR - 0xE000 C000, U2THR -
0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only)
The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the
UnTHR. The UnTHR is always Write Only.
UnTHR. The UnTHR is always Write Only.
4.3 UARTn Divisor Latch LSB Register (U0DLL - 0xE000 C000, U2DLL -
0xE007 8000, U3DLL - 0xE007 C000 when DLAB = 1) and UARTn
Divisor Latch MSB Register (U0DLM - 0xE000 C004, U2DLL -
0xE007 8004, U3DLL - 0xE007 C004 when DLAB = 1)
Divisor Latch MSB Register (U0DLM - 0xE000 C004, U2DLL -
0xE007 8004, U3DLL - 0xE007 C004 when DLAB = 1)
The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value
used to divide the APB clock (PCLK) in order to produce the baud rate clock, which must
be 16
used to divide the APB clock (PCLK) in order to produce the baud rate clock, which must
be 16
× the desired baud rate. The UnDLL and UnDLM registers together form a 16 bit
divisor where UnDLL contains the lower 8 bits of the divisor and UnDLM contains the
Table 378: UARTn Receiver Buffer Register (U0RBR - address 0xE000 C000,
U2RBR - 0xE007 8000, U3RBR - 0E007 C000 when DLAB = 0, Read Only) bit
description
description
Bit
Symbol
Description
Reset Value
7:0
RBR
The UARTn Receiver Buffer Register contains the oldest
received byte in the UARTn Rx FIFO.
received byte in the UARTn Rx FIFO.
Undefined
Table 379: UART0 Transmit Holding Register (U0THR - address 0xE000 C000,
U2THR - 0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only) bit
description
description
Bit
Symbol
Description
Reset Value
7:0
THR
Writing to the UARTn Transmit Holding Register causes the data
to be stored in the UARTn transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
to be stored in the UARTn transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
NA