Nxp Semiconductors UM10237 用户手册

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UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008 
429 of 792
NXP Semiconductors
UM10237
Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter
The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI 
interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the 
trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls 
below the trigger level. When the RDA interrupt goes active, the CPU can read a block of 
data defined by the trigger level.
The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn 
Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in 
3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will 
clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has 
been received that is not a multiple of the trigger level size. For example, if a peripheral 
wished to send a 105 character message and the trigger level was 10 characters, the 
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 
5 characters.
 
[1]
Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2]
For details see 
[3]
For details see 
[4]
For details see 
The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated 
when the UARTn THR FIFO is empty provided certain initialization conditions have been 
met. These initialization conditions are intended to give the UARTn THR FIFO a chance to 
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The 
initialization conditions implement a one character delay minus the stop bit whenever 
Table 384: UARTn Interrupt Handling
U0IIR[3:0] 
value
Priority Interrupt Type
Interrupt Source
Interrupt Reset
0001
-
None
None
-
0110
Highest RX Line Status 
/ Error
 or PE
 or BI
UnLSR Read
0100
Second RX Data 
Available
Rx data available or trigger level reached 
in FIFO (UnFCR0=1)
 
or UARTn FIFO 
drops below 
trigger level
1100
Second Character 
Time-out 
indication
Minimum of one character in the Rx 
FIFO and no character input or removed 
during a time period depending on how 
many characters are in FIFO and what 
the trigger level is set at (3.5 to 4.5 
character times).
The exact time will be:
[(word length) 
× 7 - 2] × 8 + [(trigger level 
- number of characters) 
× 8 + 1] RCLKs
0010
Third
THRE
THRE
UnIIR Read (if 
source of 
interrupt) or 
THR write