Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
438 of 792
NXP Semiconductors
UM10237
Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 0 < MULVAL
≤ 15
2. 0
≤ DIVADDVAL < 15
3. DIVADDVAL<MULVAL
The value of the U0/2/3FDR should not be modified while transmitting/receiving data or
data may be lost or corrupted.
data may be lost or corrupted.
If the U0/2/3FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
4.12.1 Baudrate calculation
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baudrate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baudrate with a
relative error of less than 1.1% from the desired one.
likely that the desired baudrate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baudrate with a
relative error of less than 1.1% from the desired one.