Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
474 of 792
NXP Semiconductors
UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
[1]
The error counters can only be written when RM in CANMOD is 1.
[2]
These registers can only be written when RM in CANMOD is 1.
The internal registers of each CAN Controller appear to the CPU as on-chip memory
mapped peripheral registers. Because the CAN Controller can operate in different modes
(Operating/Reset, see also
mapped peripheral registers. Because the CAN Controller can operate in different modes
(Operating/Reset, see also
), one has to distinguish between different internal address
definitions. Note that write access to some registers is only allowed in Reset Mode.
EWL
Error Warning Limit
R/W
CAN1EWL - 0xE004 4018
CAN2EWL - 0xE004 8018
SR
Status Register
RO
CAN1SR - 0xE004 401C
CAN2SR - 0xE004 801C
RFS
Receive frame status
R/W
CAN1RFS - 0xE004 4020
CAN2RFS - 0xE004 8020
RID
Received Identifier
R/W
CAN1RID - 0xE004 4024
CAN2RID - 0xE004 8024
RDA
Received data bytes 1-4
R/W
CAN1RDA - 0xE004 4028
CAN2RDA - 0xE004 8028
RDB
Received data bytes 5-8
R/W
CAN1RDB - 0xE004 402C
CAN2RDB - 0xE004 802C
TFI1
Transmit frame info (Tx Buffer 1)
R/W
CAN1TFI1 - 0xE004 4030
CAN2TFI1 - 0xE004 8030
TID1
Transmit Identifier (Tx Buffer 1)
R/W
CAN1TID1 - 0xE004 4034
CAN2TID1 - 0xE004 8034
TDA1
Transmit data bytes 1-4 (Tx Buffer 1)
R/W
CAN1TDA1 - 0xE004 4038
CAN2TDA1 - 0xE004 8038
TDB1
Transmit data bytes 5-8 (Tx Buffer 1)
R/W
CAN1TDB1- 0xE004 403C
CAN2TDB1- 0xE004 803C
CAN2TDB1- 0xE004 803C
CAN1TDB1 - 0xE004 403C
CAN2TDB1 - 0xE004 803C
CAN2TDB1 - 0xE004 803C
TFI2
Transmit frame info (Tx Buffer 2)
R/W
CAN1TFI2 - 0xE004 4040
CAN2TFI2 - 0xE004 8040
CAN2TFI2 - 0xE004 8040
CAN1TFI2 - 0xE004 4040
CAN2TFI2 - 0xE004 8040
CAN2TFI2 - 0xE004 8040
TID2
Transmit Identifier (Tx Buffer 2)
R/W
CAN1TID2 - 0xE004 4044
CAN2TID2 - 0xE004 8044
CAN2TID2 - 0xE004 8044
CAN1TID2 - 0xE004 4044
CAN2TID2 - 0xE004 8044
CAN2TID2 - 0xE004 8044
TDA2
Transmit data bytes 1-4 (Tx Buffer 2)
R/W
CAN1TDA2 - 0xE004 4048
CAN2TDA2 - 0xE004 8048
CAN2TDA2 - 0xE004 8048
CAN1TDA2 - 0xE004 4048
CAN2TDA2 - 0xE004 8048
CAN2TDA2 - 0xE004 8048
TDB2
Transmit data bytes 5-8 (Tx Buffer 2)
R/W
CAN1TDB2 - 0xE004 404C
CAN2TDB2 - 0xE004 804C
CAN2TDB2 - 0xE004 804C
CAN1TDB2 - 0xE004 404C
CAN2TDB2 - 0xE004 804C
CAN2TDB2 - 0xE004 804C
TFI3
Transmit frame info (Tx Buffer 3)
R/W
CAN1TFI3 - 0xE004 4050
CAN2TFI3 - 0xE004 8050
CAN2TFI3 - 0xE004 8050
CAN1TFI3 - 0xE004 4050
CAN2TFI3 - 0xE004 8050
CAN2TFI3 - 0xE004 8050
TID3
Transmit Identifier (Tx Buffer 3)
R/W
CAN1TID3 - 0xE004 4054
CAN2TID3 - 0xE004 8054
CAN2TID3 - 0xE004 8054
CAN1TID3 - 0xE004 4054
CAN2TID3 - 0xE004 8054
CAN2TID3 - 0xE004 8054
TDA3
Transmit data bytes 1-4 (Tx Buffer 3)
R/W
CAN1TDA3 - 0xE004 4058
CAN2TDA3 - 0xE004 8058
CAN2TDA3 - 0xE004 8058
CAN1TDA3 - 0xE004 4058
CAN2TDA3 - 0xE004 8058
CAN2TDA3 - 0xE004 8058
TDB3
Transmit data bytes 5-8 (Tx Buffer 3)
R/W
CAN1TDB3 - 0xE004 405C
CAN2TDB3 - 0xE004 805C
CAN2TDB3 - 0xE004 805C
CAN1TDB3 - 0xE004 405C
CAN2TDB3 - 0xE004 805C
CAN2TDB3 - 0xE004 805C
Table 418. Summary of CAN1 and CAN2 controller registers
Generic
Name
Name
Description
Access CAN1 Register
Address & Name
CAN2 Register
Address & Name
Address & Name
Table 419. Access to CAN1 and CAN2 controller registers
Generic
Name
Name
Operating Mode
Reset Mode
Read
Write
Read
Write
MOD
Mode
Mode
Mode
Mode
CMR
0x00
Command
0x00
Command
GSR
Global Status and Error
Counters
Counters
-
Global Status and Error
Counters
Counters
Error Counters only
ICR
Interrupt and Capture
-
Interrupt and Capture
-