Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
550 of 792
NXP Semiconductors
UM10237
Chapter 20: LPC24XX SSP interface SSP0/1
6.9 SSPn Interrupt Clear Register (SSP0ICR - 0xE006 8020, SSP1ICR -
0xE003 0020)
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in SSPnIMSC.
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in SSPnIMSC.
6.10 SSPn DMA Control Register (SSP0DMACR - 0xE006 8024,
SSP1DMACR - 0xE003 0024)
The SSPnDMACR register is the DMA control register.It is a read/write register.
Table 478: SSPn Masked Interrupt Status register (SSPnMIS -address 0xE006 801C,
SSP1MIS - 0xE003 001C) bit description
Bit
Symbol
Description
Reset Value
0
RORMIS
This bit is 1 if another frame was completely received while the
RxFIFO was full, and this interrupt is enabled.
RxFIFO was full, and this interrupt is enabled.
0
1
RTMIS
This bit is 1 if the Rx FIFO is not empty, has not been read for
a "timeout period", and this interrupt is enabled.
a "timeout period", and this interrupt is enabled.
0
2
RXMIS
This bit is 1 if the Rx FIFO is at least half full, and this interrupt
is enabled.
is enabled.
0
3
TXMIS
This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
interrupt is enabled.
0
7:4
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
NA
Table 479: SSPn interrupt Clear Register (SSP0ICR - address 0xE006 8020, SSP1ICR -
0xE003 0020) bit description
Bit
Symbol
Description
Reset Value
0
RORIC
Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.
RxFIFO was full” interrupt.
NA
1
RTIC
Writing a 1 to this bit clears the "Rx FIFO was not empty and
has not been read for a timeout period" interrupt.
has not been read for a timeout period" interrupt.
NA
7:2
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
NA
Table 480: SSPn DMA Control Register (SSP0DMACR - address 0xE006 8024, SSP1DMACR -
0xE003 0024) bit description
Bit
Symbol
Description
Reset
Value
Value
0
Receive DMA
Enable
(RXDMAE)
Enable
(RXDMAE)
When this bit is set to one 1, DMA for the receive FIFO is
enabled, otherwise receive DMA is disabled.
enabled, otherwise receive DMA is disabled.
0
1
Transmit DMA
Enable
(TXDMAE)
Enable
(TXDMAE)
When this bit is set to one 1, DMA for the transmit FIFO is
enabled, otherwise transmit DMA is disabled
enabled, otherwise transmit DMA is disabled
0
15:2
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
NA