Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
569 of 792
NXP Semiconductors
UM10237
Chapter 21: LPC24XX SD/MMC card interface
Note: This register should be read only when the data transfer is complete.
6.11 Status Register (MCIStatus - 0xE008 C034)
The MCIStatus register is a read-only register. It contains two types of flag:
•
Static [10:0]: These remain asserted until they are cleared by writing to the Clear
register (see
register (see
).
•
Dynamic [21:11]: These change state depending on the state of the underlying logic
(for example, FIFO full and empty flags are asserted and deasserted as data while
written to the FIFO).
(for example, FIFO full and empty flags are asserted and deasserted as data while
written to the FIFO).
shows the bit assignment of the MCIStatus register.
Table 503: Data Counter register (MCIDataCnt - address 0xE008 C030) bit description
Bit
Symbol
Description
Reset
Value
Value
15:0
DataCount Remaining data
0x0000
31:16
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA
Table 504: Status register (MCIStatus - address 0xE008 C034) bit description
Bit
Symbol
Description
Reset
Value
Value
0
CmdCrcFail
Command response received (CRC check failed).
0
1
DataCrcFail
Data block sent/received (CRC check failed).
0
2
CmdTimeOut
Command response timeout.
0
3
DataTimeOut
Data timeout.
0
4
TxUnderrun
Transmit FIFO underrun error.
0
5
RxOverrun
Receive FIFO overrun error.
0
6
CmdRespEnd
Command response received (CRC check passed).
0
7
CmdSent
Command sent (no response required).
0
8
DataEnd
Data end (data counter is zero).
0
9
StartBitErr
Start bit not detected on all data signals in wide bus mode. 0
10
DataBlockEnd
Data block sent/received (CRC check passed).
0
11
CmdActive
Command transfer in progress.
0
12
TxActive
Data transmit in progress.
0
13
RxActive
Data receive in progress.
0
14
TxFifoHalfEmpty Transmit FIFO half empty.
0
15
RxFifoHalfFull
Receive FIFO half full.
0
16
TxFifoFull
Transmit FIFO full.
0
17
RxFifoFull
Receive FIFO full.
0
18
TxFifoEmpty
Transmit FIFO empty.
0
19
RxFifoEmpty
Receive FIFO empty.
0