Nxp Semiconductors UM10237 用户手册

UM10237_2

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The I

2

C0/1/2 interfaces are configured using the following registers:

1. Power: In the PCONP register (

), set bit PCI2C0/1/2.

Remark: On reset, all I

2

C interfaces are enabled (PCI2C0/1/2 = 1).

2. Clock: In PCLK_SEL0 select PCLK_I2C0; in PCLK_SEL1 select PCLK_I2C1/2 (see 

3. Pins: Select I

2

C pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to 

). 

Remark: I

2

C0 pins SDA0 and SCL0 are open-drain outputs for I

2

C-bus compliance 

(see 

).

4. Interrupts are enabled in the VIC using the VICIntEnable register (

5. Initialization: see 

 and 

.

Standard I

2

C compliant bus interfaces that may be configured as Master, Slave, or 

Master/Slave.

Arbitration between simultaneously transmitting masters without corruption of serial 
data on the bus.

Programmable clock to allow adjustment of I

2

C transfer rates.

Bidirectional data transfer between masters and slaves.

Serial clock synchronization allows devices with different bit rates to communicate via 
one serial bus.

Serial clock synchronization can be used as a handshake mechanism to suspend and 
resume serial transfer.

The I

2

C bus may be used for test and diagnostic purposes.

Interfaces to external I

2

C standard parts, such as serial RAMs, LCDs, tone generators, 

etc.

A typical I

2

C bus configuration is shown in 

. Depending on the state of the 

direction bit (R/W), two types of data transfers are possible on the I

2

C bus:

Data transfer from a master transmitter to a slave receiver. The first byte transmitted 
by the master is the slave address. Next follows a number of data bytes. The slave 
returns an acknowledge bit after each received byte.