Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
600 of 792
NXP Semiconductors
UM10237
Chapter 22: LPC24XX I
2
C interfaces I
2
C0/1/2
9.6 Some special cases
The I
2
C hardware has facilities to handle the following special cases that may occur
during a serial transfer:
9.7 Simultaneous repeated START conditions from two masters
A repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
repeated START condition (see
receiver modes. A special case occurs if another master simultaneously generates a
repeated START condition (see
). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
If the I
2
C hardware detects a repeated START condition on the I
2
C bus before generating
a repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I
generated. If another master frees the bus by generating a STOP condition, the I
2
C block
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
transfer can commence.
9.8 Data transfer after loss of arbitration
Arbitration may be lost in the master transmitter and master receiver modes (see
). Loss of arbitration is indicated by the following states in I2STAT; 0x38,
0x68, 0x78, and 0xB0 (see
).
If the STA flag in I2CON is set by the routines which service these states, then, if the bus
is free again, a START condition (state 0x08) is transmitted without intervention by the
CPU, and a retry of the total serial transfer can commence.
is free again, a START condition (state 0x08) is transmitted without intervention by the
CPU, and a retry of the total serial transfer can commence.
9.9 Forced access to the I
2
C bus
In some applications, it may be possible for an uncontrolled source to cause a bus
hang-up. In such situations, the problem may be caused by interference, temporary
interruption of the bus or a temporary short-circuit between SDA and SCL.
hang-up. In such situations, the problem may be caused by interference, temporary
interruption of the bus or a temporary short-circuit between SDA and SCL.
Table 529. Miscellaneous states
Status
Code
(I2CSTAT)
Code
(I2CSTAT)
Status of the I
2
C bus
and hardware
Application software response
Next action taken by I
2
C hardware
To/From I2DAT
To I2CON
STA STO SI
AA
0xF8
No relevant state
information available;
SI = 0.
information available;
SI = 0.
No I2DAT action
No I2CON action
Wait or proceed current transfer.
0x00
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
2
C block
to enter an undefined
state.
state.
No I2DAT action
0
1
0
X
Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
the MST or addressed SLV modes. In all
cases, the bus is released and the I
2
C
block is switched to the not addressed
SLV mode. STO is reset.
SLV mode. STO is reset.