Nxp Semiconductors UM10237 用户手册

UM10237_2

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next falling edge of the transmitting clock after a WS change. In stereo mode when WS is 
low left data is transmitted and right data when WS is high. In mono mode the same data 
is transmitted twice, once when WS is low and again when WS is high.

In master mode (ws_sel = 0), word select is generated internally with a 9 bit counter. 
The half period count value of this counter can be set in the control register.

In slave mode (ws_sel = 1) word select is input from the relevant bus pin.

When an I

2

S bus is active, the word select, receive clock and transmit clock signals 

are sent continuously by the bus master, while data is sent continuously by the 
transmitter.

Disabling the I

2

S can be done with the stop or mute control bits separately for the 

transmit and receive.

The stop bit will disable accesses by the transmit channel or the receive channel to 
the FIFOs and will place the transmit channel in mute mode.

The mute control bit will place the transmit channel in mute mode. In mute mode, the 
transmit channel FIFO operates normally, but the output is discarded and replaced by 
zeroes. This bit does not affect the receive channel, data reception can occur 
normally.

 

I2SRX_CLK

Input/Output Receive Clock. A clock signal used to synchronize the transfer of 

data on the receive channel. It is driven by the master and received 
by the slave. Corresponds to the signal SCK in the I

2

S bus 

specification.

I2SRX_WS

Input/Output Receive Word Select. Selects the channel from which data is to be 

received. It is driven by the master and received by the slave. 
Corresponds to the signal WS in the I

2

S bus specification.

WS = 0 indicates that data is being received by channel 1 (left 
channel).

WS = 1 indicates that data is being received by channel 2 (right 
channel).

I2SRX_SDA

Input/Output Receive Data. Serial data, received MSB first. It is driven by the 

transmitter and read by the receiver. Corresponds to the signal SD 
in the I

2

S bus specification.

I2STX_CLK

Input/Output Transmit Clock. A clock signal used to synchronize the transfer of 

data on the transmit channel. It is driven by the master and received 
by the slave. Corresponds to the signal SCK in the I

2

S bus 

specification.

I2STX_WS

Input/Output Transmit Word Select. Selects the channel to which data is being 

sent. It is driven by the master and received by the slave. 
Corresponds to the signal WS in the I

2

S bus specification.

WS = 0 indicates that data is being sent to channel 1 (left channel).

WS = 1 indicates that data is being sent to channel 2 (right channel).

I2STX_SDA

Input/Output Transmit Data. Serial data, sent MSB first. It is driven by the 

transmitter and read by the receiver. Corresponds to the signal SD 
in the I

2

S bus specification.