Nxp Semiconductors UM10237 用户手册

UM10237_2

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The Timer0/1/2/3 peripherals are configured using the following registers:

1. Power: In the PCONP register (

), set bits PCTIM0/1/2/3.

Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled 
(PCTIM2/3 = 0).

2. Peripheral clock: In the PCLK_SEL0 register (

), select PCLK_TIMER0/1; in 

the PCLK_SEL1 register (

), select PCLK_TIMER2/3.

3. Pins: Select Timer0/1/2/3 pins and pin modes in registers PINSELn and PINMODEn 

(see 

). 

4. Interrupts: See register T0/1/2/3MCR (

) and T0/1/2/3CCR 

) for match and capture events. Interrupts are enabled in the VIC using 

the VICIntEnable register (

).

Remark: The four Timer/Counters are identical except for the peripheral base address. A 
minimum of two Capture inputs and two Match outputs are pinned out for all four timers, 
with a choice of several pins for each. Timer 1 brings out a third Match output, while 
Timers 2 and 3 bring out all four Match outputs.

A 32 bit Timer/Counter with a programmable 32 bit Prescaler.

Counter or Timer operation

Up to four 32 bit capture channels per timer, that can take a snapshot of the timer 
value when an input signal transitions. A capture event may also optionally generate 
an interrupt.

Four 32 bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

Up to four external outputs corresponding to match registers, with the following 
capabilities:

– Set low on match.

– Set high on match.

– Toggle on match.

– Do nothing on match.

Interval Timer for counting internal events.

Pulse Width Demodulator via Capture inputs.