Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
646 of 792
NXP Semiconductors
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
5
Enable PWM
Match 5 Latch
Match 5 Latch
PWM MR5 register update control. See bit 0 for details.
0
6
Enable PWM
Match 6 Latch
Match 6 Latch
PWM MR6 register update control. See bit 0 for details.
0
7
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
value read from a reserved bit is not defined.
NA
Table 564: PWM Latch Enable Register (PWM0LER - address 0xE001 4050 and PWM1LER
address 0xE001 8050) bit description
Bit Symbol
Description
Reset
Value
Value