Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

3. Pins: Select data, address, and control pins and their modes in PINSEL6/8/9 and 

PINMODE6/8/9 (see 

). 

4. Configuration: see 

 to 

The LPC2400 External Memory Controller (EMC) is an ARM PrimeCell™ MultiPort 
Memory Controller peripheral offering support for asynchronous static memory devices 
such as RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate 
SDRAM. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant 
peripheral.

Dynamic memory interface support including Single Data Rate SDRAM.

Asynchronous static memory device support including RAM, ROM, and Flash, with or 
without asynchronous page mode.

Low transaction latency.

Read and write buffers to reduce latency and to improve performance.

8 bit, 16 bit, and 32 bit wide static memory support.

16 bit and 32 bit wide chip select SDRAM memory support.

Static memory features include:

– Asynchronous page mode read

– Programmable wait states

– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

Four chip selects for synchronous memory and four chip selects for static memory 
devices.

Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

Dynamic memory self-refresh mode controlled by software.

Controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts. 
That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per 
device.

Separate reset domains allow the for auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

 shows a block diagram of the EMC.