Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

Code Read Protection is a mechanism that allows user to enable different levels of 
security in the system so that access to the on-chip Flash and use of the ISP can be 
restricted. When needed, CRP is invoked by programming a specific pattern in Flash 
location at 0x000001FC. IAP commands are not affected by the code read protection.

Starting with bootloader version 3.2 three levels of CRP are implemented. Earlier 
bootloader versions had only CRP2 option implemented.

 

CRP1

0x12345678

Access to chip via the JTAG pins is disabled. This mode allows partial 
Flash update using the following ISP commands and restrictions:

Write to RAM command can not access RAM below 0x40000200

Copy RAM to Flash command can not write to Sector 0

Erase command can erase Sector 0 only when all sectors are 
selected for erase

Compare command is disabled

This mode is useful when CRP is required and Flash field updates are 
needed but all sectors can not be erased. Since compare command is 
disabled in case of partial updates the secondary loader should 
implement checksum mechanism to verify the integrity of the Flash.

CRP2

0x87654321

Access to chip via the JTAG pins is disabled. The following ISP 
commands are disabled:

Read Memory

Write to RAM

Go

Copy RAM to Flash

Compare

When CRP2 is enabled the ISP erase command only allows erasure of 
all user sectors. 

CRP3

0x43218765

Access to chip via the JTAG pins is disabled. ISP entry by pulling P2.10 
LOW is disabled if a valid user code is present in Flash sector 0.

This mode effectively disables ISP overide using P2.10 pin. It is up to the 
user’s application to provide need Flash update mechanism using IAP 
calls or call reinvoke ISP command to enable Flash update via UART0.