Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
95 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.27 Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3 -
0xFFE0 8218, 238, 258, 278)
The EMCStaticWaitTurn0-3 registers enable you to program the number of bus
turnaround cycles. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
turnaround cycles. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
shows the bit assignments for the EMCStaticWaitTurn0-3 registers.
To prevent bus contention on the external memory data bus, the WAITTURN field controls
the number of bus turnaround cycles added between static memory read and write
accesses. The WAITTURN field also controls the number of turnaround cycles between
static memory and dynamic memory accesses.
the number of bus turnaround cycles added between static memory read and write
accesses. The WAITTURN field also controls the number of turnaround cycles between
static memory and dynamic memory accesses.
11. External memory interface
External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW
bits in corresponding EMCStaticConfig register).
bits in corresponding EMCStaticConfig register).
If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used
as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required.
However, 8 bit wide memory banks do require all address lines down to A0. Configuring
A1 and/or A0 line(s) to provide address or non-address function is accomplished using the
Pin Function Select Register (see
as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required.
However, 8 bit wide memory banks do require all address lines down to A0. Configuring
A1 and/or A0 line(s) to provide address or non-address function is accomplished using the
Pin Function Select Register (see
).
Table 94.
Static Memory Write Delay registers0-3 (EMCStaticWaitWr - address 0xFFE0 8214,
0xFFE0 8234, 0xFFE0 8254, 0xFFE0 8274) bit description
0xFFE0 8234, 0xFFE0 8254, 0xFFE0 8274) bit description
Bit
Symbol
Value Description
Reset
Value
Value
4:0
Write wait states
(WAITWR)
(WAITWR)
SRAM wait state time for write accesses after the first
read:
read:
0x1F
0x0 -
0x1E
0x1E
(n + 2) CCLK cycle write access time. The wait state time
for write accesses after the first read is WAITWR (n + 2) x
tCCLK.
for write accesses after the first read is WAITWR (n + 2) x
tCCLK.
0x1F
33 CCLK cycle write access time (POR reset value).
31:5
-
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
reserved bits. The value read from a reserved bit is not
defined.
NA
Table 95.
Static Memory Trun Round Delay registers0-3 (EMCStaticWaitTurn0-3 - address
0xFFE0 8218, 0xFFE0 8238, 0xFFE0 8258, 0xFFE0 8278) bit description
0xFFE0 8218, 0xFFE0 8238, 0xFFE0 8258, 0xFFE0 8278) bit description
Bit
Symbol
Value Description
Reset
Value
Value
3:0
Bus turnaround
cycles
(WAITTURN)
cycles
(WAITTURN)
0x0 -
0xE
0xE
(n + 1) CCLK turnaround cycles. Bus turnaround time is
(WAITTURN + 1) x tCCLK.
(WAITTURN + 1) x tCCLK.
0xF
0xF
16 CCLK turnaround cycles (POR reset value).
31:4
-
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
reserved bits. The value read from a reserved bit is not
defined.
NA