Renesas SH7700 Series 用户手册

 

 

18 

In addition to BREAKPOINT functions, the emulator has Break Condition functions.  Three types 
of conditions can be set under Break Condition 1, 2, 3.  Table 2.4 lists these conditions of Break 
Condition. 

Address bus condition (Address) 

Breaks when the SH7710 address bus value or the program 
counter value matches the specified value. 

Data bus condition (Data) 

Breaks when the SH7710 data bus value matches the 
specified value.  Byte, word, or longword can be specified as 
the access data size. 

X-Bus or Y-Bus condition (Address 
and data) 

Breaks when the X-Bus or Y-Bus address bus or data bus 
matches the specified value. 

Bus state condition  
(Bus State) 

There are two bus state condition settings: 

Read/Write condition: Breaks when the SH7710 RD or 
RDWR signal level matches the specified condition. 

Bus state condition: Breaks when the operating state in an 
SH7710 bus cycle matches the specified condition. 

Types of buses that can be specified are listed below. 

•

 

L-bus (CPU-ALL): Indicates an instruction fetch and data 

access, including a hit to the cache memory. 

•

 

L-bus (CPU-Data): Indicates a data access by the CPU, 

including a hit to the cache memory. 

•

 

I-bus (CPU.DMA): Indicates a CPU cycle when the 

cache memory is not hit, and a data access by the 
DMA. 

Internal I/O break condition 

Breaks when the SH7710 accesses the internal I/O. 

LDTLB instruction break condition 

Breaks when the SH7710 executes the LDTLB instruction. 

Count 

Breaks when the conditions set are satisfied the specified 
number of times. 

 

Note:  When X/Y-RAM is accessed from the P0 space, the I-bus must be selected, and when 

accessed from the P2 space, the L-bus must be selected. When cache fill cycle is acquired, 
the I-bus must be selected.