Renesas 4514 用户手册

1-42

4513/4514 Group User’s Manual

Q1

3

Q1

2

Q1

1

Q1

0

A-D control register Q1

Not used

Analog input pin selection bits (Note 2)

at reset : 0000

2

at RAM back-up : state retained

0

1

Q1

2

0

0

0

0

1

1

1

1

Q1

1

0

0

1

1

0

0

1

1

This bit has no function, but read/write is enabled.

Selected pins

A

IN0

A

IN1

A

IN2

A

IN3

A

IN4

 (Not available for the 4513 Group)

A

IN5

 (Not available for the 4513 Group)

A

IN6

 (Not available for the 4513 Group)

A

IN7

 (Not available for the 4513 Group)

at reset : 0000

2

Q2

3

Q2

2

Q2

1

Q2

0

A-D control register Q2

A-D conversion mode

Comparator mode

P4

3

, P4

2

(read/write enabled for the 4513 Group)

A

IN7

, A

IN6

/P4

3

, P4

2

(read/write enabled for the 4513 Group)

P4

1

(read/write enabled for the 4513 Group)

A

IN5

/P4

1

(read/write enabled for the 4513 Group)

P4

0

(read/write enabled for the 4513 Group)

A

IN4

/P4

0

(read/write enabled for the 4513 Group)

A-D operation mode selection bit

P4

3

/A

IN7

 and P4

2

/A

IN6

 pin function selec-

tion bit (Not used for the 4513 Group)

P4

1

/A

IN5

 pin function selection bit

(Not used for the 4513 Group)

P4

0

/A

IN4

 pin function selection bit

(Not used for the 4513 Group)

at RAM back-up : state retained

0

1

0

1

0

1

0

1

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: Select A

IN4

–A

IN7

 with register Q1 after setting register Q2.

Q1

0

0

1

0

1

0

1

0

1

The A-D conversion mode is set by setting the bit 3 of register Q2 to “0.”

Register AD stores the A-D conversion result of an analog input in

10-bit digital data format. The contents of the high-order 8 bits of

this register can be stored in register B and register A with the

TABAD instruction. The contents of the low-order 2 bits of this reg-

ister can be stored into the high-order 2 bits of register A with the

TALA instruction. However, do not execute this instruction during A-

D conversion.

When the contents of register AD is n, the logic value of the com-

parison voltage V

ref

 generated from the built-in DA converter can

be obtained with the reference voltage V

DD

 by the following for-

mula:

Logic value of comparison voltage V

ref

V

ref

 =

✕

 n

n: The value of register AD (n = 0 to 1023)

V

DD

1024

A-D conversion starts when the ADST instruction is executed.  The

conversion result is automatically stored in the register AD.

Register Q1 is used to select one of analog input pins. The 4513

Group does not have A

IN4

–A

IN7

. Accordingly, do not select these

pins with register Q1.

Register Q2 is used to select the pin function of P4

0

/A

IN4

, P4

1

/

A

IN5

, P4

2

/A

IN6

, and P4

3

/A

IN7

. The A-D conversion mode is se-

lected when the bit 3 of register Q2 is “0,” and the comparator

mode is selected when the bit 3 of register Q2 is “1.” After set this

register, select the analog input with register Q1.

Even when register Q2 is used to set the pins for analog input,

P4

0

/A

IN4

–P4

3

/A

IN7

 continue to function as P4

0

–P4

3

 I/O. Accord-

ingly, when any of them are used as I/O port P4 and others are

used as analog input pins, make sure to set the outputs of pins that

are set for analog input to “1.” Also, for the port input, the port input

function of the pin functions as analog input is undefined.

R/W

R/W

A-D conversion completion flag (ADF) is set to “1” when A-D con-

version completes. The state of ADF flag can be examined with the

skip instruction (SNZAD). Use the interrupt control register V2 to

select the interrupt or the skip instruction.

The ADF flag is cleared to “0” when the interrupt occurs or when

the next instruction is skipped with the skip instruction.