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Section 3 DSP Operation
Rev. 4.00 Sep. 14, 2005 Page 109 of 982
REJ09B0023-0400
3.1.5 Shift
Operations
Shift operations can use either register or immediate value as the shift amount operand. Other
source and destination operands are specified by the register. There are two kinds of shift
operations. Table 3.7 shows the variation of this type of operation. The correspondence between
each operand and registers, except for immediate operands, is the same as the ALU fixed-point
operations as shown in table 3.2.
source and destination operands are specified by the register. There are two kinds of shift
operations. Table 3.7 shows the variation of this type of operation. The correspondence between
each operand and registers, except for immediate operands, is the same as the ALU fixed-point
operations as shown in table 3.2.
Table 3.7
Variation of Shift Operations
Mnemonic
Function
Source 1
Source 2
Destination
PSHA Sx, Sy, Dz
Arithmetic shift
Sx
Sy
Dz
PSHL Sx, Sy, Dz
Logical shift
Sx
Sy
Dz
PSHA #Imm1, Dz Arithmetic shift with
immediate.
Dz Imm1
Dz
PSHL #Imm2, Dz Logical shift with
immediate.
Dz Imm2
Dz
Note: –32 <= Imm1 <= +32, –16 <= Imm2 <= +16
Arithmetic Shift: Figure 3.9 shows the arithmetic shift operation flow.
DSR
GT
Z
N
V
DC
Updated
7g
0g 31
16 15
0
Sy
7g
0g 31
16 15
0
0
Shift out
Shift out
(MSB copy)
Ignored
Left Shift
Right Shift
7g
0g 31
23 22
16
Imm1
6
0
15
0
Shift amount data:
(Source 2)
(Source 2)
> = 0
< 0
+32 to –32
Figure 3.9 Arithmetic Shift Operation Flow
Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the
base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit
parts when a register not providing the guard-bit parts is specified as the source operand.
When a register not providing the guard-bit parts is specified as a destination operand, the
lower 32 bits of the operation result are input into the destination register.
parts when a register not providing the guard-bit parts is specified as the source operand.
When a register not providing the guard-bit parts is specified as a destination operand, the
lower 32 bits of the operation result are input into the destination register.