Renesas HD6417641 用户手册

Section 3   DSP Operation 

Rev. 4.00  Sep. 14, 2005  Page 124 of 982 

REJ09B0023-0400 

 

This LSI prepares a special control mechanism for efficient repeat loop control. An instruction 
SETRC sets the repeat times into the repeat counter RC (12 bits), and an execution mode in which 
a program loop executes repetitively until RC is equal to 1. After completion of the repeat 
instructions, the RC value becomes 0. 

Repeat start address register RS keeps the start address of a repeat loop. Repeat end register RE 
keeps the repeat end address. (There are some exceptions. See note, Actual Implementation 
Options.) Repeat counter RC keeps the number of repeat times. In order to perform loop control, 
the following steps are required. 

Step 1)  Set loop start address into RS 

Step 2)  Set loop end address into RE 

Step 3)  Set repeat counter into RC 

Step 4)  Start repeat control 

 

To do steps 1 and 2, use the following instructions:  

LDRS @(disp,PC) 

LDRE @(disp,PC) 

 

For steps 3 and 4, use the SETRC instruction. An operand of SETRC is an immediate value or one 
of the general-purpose registers that will specify the repeat times.  

SETRC #imm; 

#imm->RC, enable repeat control 

SETRC Rm;  

Rm->RC, enable repeat control